Intel® E8500 ChipsetTechnical Documents

The Intel® E8500 chipset is built architecturally around three major components: Intel® E8500 chipset North Bridge (NB), Intel® E8500 chipset eXternal Memory Bridge (XMB), and the Intel® I/O Controller Hub 5 (ICH5). The NB provides the processor front side bus for up to 4 64-bit Intel® Xeon® processor MP, Independent Memory Interface for up to 4 XMB, hub interface 1.5 for ICH5, and an I/O subsystem based on one x4 PCI Express Link and three x8 PCI Express* Links.

File Type/Size:  PDF 5163KB

The XMB is an intelligent memory controller that bridges the IMI and DDR interfaces. Each XMB connects to one of the Intel® E8500 chipset North Bridge (NB) IMI interfaces. The Intel® E8500 chipset may operate with 1 to 4 XMBs. This document describes the basic features, modes and registers supported by the XMB, as well as signal descriptions.

File Type/Size:  PDF 3471KB

This datasheet is intended for Original Equipment Manufacturers and BIOS vendors creating Intel ICH5-based products. This datasheet assumes a working knowledge of the vocabulary and principles of USB, IDE, AC ?97, SMBus, PCI, ACPI and LPC.

File Type/Size:  PDF 7772KB

• Intel® 875P Chipset: Intel® 82875P Memory Controller Hub (MCH) Datasheet
• Intel® 82801EB I/O Controller Hub 5 (ICH5)/Intel® 82801ER I/O Controller Hub 5 R (ICH5R) Specification Update

The Intel® 6700PXH 64-bit PCI Hub is targeted for the server market. It is a peripheral component that performs PCI bridging functions between the PCI Express* interface and the PCI Bus. It contains two PCI bus interfaces that can be independently configured to operate in PCI (33 or 66 MHz) or PCI-X Mode 1 (66, 100, or 133 MHz), for either 32 or 64 bit PCI devices. It further supports the new PCI Standard Hot-Plug Controller and Subsystem Specification Revision 1.0.

File Type/Size:  PDF 2271KB

This document discusses thermal management and measurement techniques, and provides details on the Intel-enabled thermal solutions for the Intel® E8500 chipset North Bridge (NB) and eXternal Memory Bridge (XMB).

File Type/Size:  PDF 1786KB

This document provides an understanding of the operating limits of the Intel 82801EB I/O Controller Hub 5 (ICH5) / Intel 82801ER I/O Controller Hub 5 R (ICH5R) components and presents the conditions and requirements to properly design a cooling solution for systems that implement the ICH5.

File Type/Size:  PDF 309KB

• Intel® 82801EB I/O Controller Hub 5 (ICH5) and Intel® 82801ER I/O Controller Hub 5 R (ICH5R) Datasheet

This design guide specifies the thermal operating limits and mechanical requirements of the Intel® 6700PXH 64-bit PCI Hub. It provides guidance on how to properly design a cooling solution for systems that implement the PXH. The design guide also presents a reference Heat Sink design that meets the thermal and mechanical requirements of the Intel® 6700PXH 64-bit PCI Hub.

File Type/Size:  PDF 605KB

The Intel® E8500 chipset is the highest performance, most scalable platform offering in the 64-bit Intel® Xeon™ processor family.

File Type/Size:  PDF 290KB

This document is a compilation of errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems and tools.

File Type/Size:  PDF 114KB

This document is a compilation of errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems and tools.

File Type/Size:  PDF 74KB

This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.

File Type/Size:  PDF 138KB

This public document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools. This location contains the most current Specification Update. The revision number is indicated by the last two digits.

File Type/Size:  PDF 233KB

• Intel® 82801EB I/O Controller Hub 5 (ICH5) / Intel® 82801ER I/O Controller Hub 5 R (ICH5R) Datasheet