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Low-Power Module Memory Bus Simulation Methodology
This application note describes a simulation methodology for interfacing memory signals from the Low-Power Module to the 100-MHz Unbuffered SDRAM Dual In-Line Memory Modules (SDRAM DIMM). The models used to drive the simulation tool are based on the I/O Buffer Industry Standard (IBIS). Note: The simulation methodology in this application note is based on 100 MHz SDRAM DIMM designs; however, the same methodology applies to 66 MHz SDRAM DIMM designs.
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