In a recent application, we stated that as long as TGH remains valid, the 8253 "will not lock up". If the GATE is pulsed during counting with TGS violating the spec and TGH meeting the spec, it is uncertain that count will be loaded from the CR to the CE on the 8253. This is not the case with the 8254. This analysis will clarify the behavior of the 8254 Programmable Interface Timer if the GATE inputs violate the TGS/TGH specs.

OUT is initially high. In Mode 2 OUT goes low for one CLK pulse when the initial count has decremented to 1. In Mode 3, when half of the initial count has expired, OUT goes low for the duration of the count. GATE = 1 enables count, GATE = 0 disables count.

If the GATE is pulsed during counting with TGS/TGH within the required margins, OUT is set high immediately. The initial count will be loaded from the CR to the CE (see figure 5 in the Data Sheet) on the next falling edge of CLK (see A in figure 1).

If the GATE is pulsed during counting with both TGS/TGH violating the spec there is no guarantee that count will or will not be loaded. In this case, the internal logic is not able to resolve the state of the GATE.

If the GATE is pulsed during counting with TGS violating the spec but TGH meeting the spec, the initial count will be loaded on either the first or second falling edge of CLK (A or B in Figure 2). In this case, the internal logic can resolve the state of the GATE, but not in time.

The internal logic provides a way to ensure recognition of the GATE on the rising edge of the CLK. In Modes 2 and 3, the 8254 is both edge and level triggered. In the second case, where both specs are violated, neither the edge nor the level detector will detect the GATE going high, therefore, the count may not be loaded. As long as TGH is valid, the level detector will detect GATE going high even though the edge detector doesn't. This allows count to be loaded on either the first or second count, but it is not guaranteed on which falling edge, A or B (Figure 2), the loading will occur.