IntelŪ 848P Chipset Platform Design Guide Update

For Use with the IntelŪ PentiumŪ 4 Processor with 512-KB L2 Cache on 0.13 Micron Process and the IntelŪ PentiumŪ 4 Processor on 90 nm Process

This document is a compilation of updates to the general design considerations; schematic, layout, and routing updates; and documentation changes. This document is intended for hardware system manufacturers and for software developers of applications, operating systems, and tools.

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  • IntelŪ 848P Chipset Platform Design Guide, 253576

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