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Features & Benefits |
Product Package
The Intel® E7501 chipset represents the next step in high performance chipset technology. The Intel E7501 chipset supports dual-processor platforms optimized for the Intel® Xeon® processor, and the Low Voltage Intel® Xeon® processor, and Intel NetBurst® microarchitecture. It also supports uni-processor platforms optimized for the Intel® Pentium® M Processor. The Intel E7501 chipset design delivers maximized system bus, memory, and I/O bandwidth to enhance performance, scalability, and end-user productivity while providing a smooth transition to next generation technologies.
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The Intel E7501 chipset utilizes a modular design and offers platform implementation flexibility to meet the expanding needs of uni- and dual-processor embedded computing applications through three core components:
The Intel® E7501 Memory Controller Hub (MCH) is the central hub for all data passing through core system elements such as the Intel Xeon processors or the Intel Pentium M processors via the system bus interface, the memory via memory interface, and both the 64-bit PCI/PCI-X and I/O controller hubs via Intel® Hub Interfaces. The Intel E7501 chipset delivers compelling performance at 4.3 GB/s of bandwidth across the 400/533 MHz system bus and up to 4.3 GB/s of bandwidth across two high performance DDR memory channels, or 2.2 GB/s bandwidth across one DDR memory channel. The MCH also allows several high-bandwidth I/O configuration options for a total of 3.2 GB/s of I/O bandwidth. Together, these features deliver high-throughput system performance.
The Intel® 82870P2 64-bit PCI/PCI-X Controller Hub 2 (P64H2) connects to the MCH through a point-to-point Hub Interface 2.0 connection. Up to three P64H2 devices can be attached to the MCH, each providing an I/O bandwidth over 1.066 GB/s for a total of 3.2 GB/s of I/O bandwidth. Each P64H2 contains two independent 64-bit PCI-X interfaces and two PCI hot plug controllers, one per PCI-X interface. Each 64-bit PCI-X segment supports multiple PCI-X slots for high bandwidth connectivity of next-generation components such as Intel® Gigabit Ethernet adapters and Intel® I/O processors.
The Intel® 82801CA I/O Controller Hub3-S (ICH3-S) connects to the MCH through a point-to-point Hub Interface 1.5 connection. The ICH3-S provides legacy I/O interfaces through integrated
features including a two-channel Ultra ATA/100 bus master IDE controller and three USB controllers for up to six USB 1.0 ports. The ICH3-S also offers an integrated System Manageability Bus 2.0 (SMBus 2.0) controller, an integrated LAN controller, as well as AC'97 2.2-compliant and PCI 2.2-compliant interfaces.
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| Supports one or two Intel® Xeon® processors or Low Voltage Intel® Xeon® processors |
Intel NetBurst® microarchitecture and the Hyper-Threading Technology of the Intel Xeon processor combine to deliver world-class performance. |
| Supports one Intel® Pentium® M Processor |
New microarchitecture supports low power and high performance. |
| 400/533 MHz system bus capability |
Up to 4.3 GB/s system bus bandwidth for increased memory and I/O throughput. |
| Intel® Hub Architecture 2.0 connection to the Memory Controller Hub (MCH) |
Point-to-point connection between the MCH and up to three P64H2 devices provides up to 3.2 GB/s of bandwidth. Error Correction Code (ECC) protection, coupled with high data transfer rates, supports I/O segments with greater reliability and faster access to high-speed networks. |
| PCI/PCI-X 64-bit controller hub |
Next-generation PCI/PCI-X performance and significantly enhances platform flexibility. Two independent 64- bit, 133 MHz PCI-X segments and two hot-plug controllers (one per segment) for each P64H2 allow up to six PCI-X buses per system. |
| Single/dual-channel DDR266 memory interface |
Maximum memory bandwidth of 4.3 GB/s through a 144-bit wide, 266 MHz Double Data Rate SDRAM memory interface with densities up to 512 megabits. |
| Advanced Platform Reliability, Availability, Serviceability, Useability and Management (RASUM) |
Memory ECC with Intel® x4 Single Device Data Correction++, hardware memory scrubbing, MCH SMBus target interface, hub interface ECC, and the availability of enhanced error status information deliver increased platform reliability. |
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| ++ In a x4 DDR memory device, the Intel® x4 Single Device Data Correction (x4 SDDC), provides error detection and correction for 1,2,3, or 4 data bits within that single device and provides error detection, up to 8 data bits, within two devices in a dual channel configuration. Single channel provides error detection and correction for 1 data bit and provides error detection, up to 2 bits, within two devices. |
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| Product |
Package |
| Intel® E7501 Memory Controller Hub (MCH) |
1005 Flip Chip-Ball Grid Array (FC-BGA) |
Intel® 82801CA Integrated Controller Hub
(ICH3-S) |
421 Ball Grid Array (BGA) |
| Intel® 82870P2 64-bit PCI/PCI-X Controller (P64H2) |
567 Flip Chip-Ball Grid Array (FC-BGA) |
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