| Up to 800 MHz CPU, Integrated PCI Express* to PCI-X Bridge and High-Bandwidth Memory Controller Deliver Superior Performance |
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The IntelŽ IOP331 is a highly integrated I/O system on a chip for I/O-intensive storage, networking, communications, and embedded applications. The IOP331 features an 800 MHz CPU, high-performance internal bus, dual-ported memory controller, a high-bandwidth PCI-X to PCI-X Bridge, and an improved interrupt controller to provide a high-performance, highly integrated processor solution. Target applications include PCI/PCI-X host-based adapters (RAID cards, iSCSI cards, FC cards, Security/SSL NICs, etc), control plane and system controller applications utilizing PCI/PCI-X as a system interconnect and/or backplane Virtual Private Network devices, video servers, Network gateways, Network Attached Storage, External Storage Arrays), PCI/PCI-X-based line cards (VoIP, Routers, etc.), and a host of other applications that require a highly integrated, high-performance system on a chip processor. The Intel IOP331 also includes hardware acceleration for Intelligent RAID6 via a P +Q implementation. Larger RAID arrays, increasing disk densities and the introduction of Serial ATA in business applications are creating a growing need for better performing RAID 6 implementations.
As Intel's sixth-generation I/O processor, the IOP331 continues to build on Intel's strength in delivering high-performance, low-power Intel XScaleŽ technology processors. It integrates IntelŽ Super-Pipelined RISC Technology with 7-stage integer/8-stage memory super-pipelined core, 32 Kbyte data and instruction caches and operates up to 800 MHz. The IOP331 is code compatible with the IntelŽ IOP321 I/O Processor, other Intel XScale core processors, and ARM*-based devices, simplifying code porting from existing designs. It is compliant with the ARM v5TE* instruction set (excluding the floating-point instruction set). The internal bus operates at 266 MHz and offers internal bandwidth of up to 2.1 Gbytes/second.
The IOP331 provides ultra-fast memory transactions due to its Double Data Rate (DDR) SDRAM dual-ported memory controller that supports up to 2 GB of DDR 333 MHz memory or 1 GB of DDRII 400 MHz memory. Registered and unbuffered DDR 333 and registered DDRII 400 DIMMs can be used with IOP331. The memory controller supports 32-bit or 64-bit memory subsystems with or without ECC. The IOP331 features a new dual-ported memory controller that provides both a direct port from the CPU to memory (core port) and a port from the ATU/internal bus to memory (internal bus port). This allows both CPU memory accesses and data movement to and from the internal bus to occur providing high overall system performance. Performance optimizations can be made by using the memory controller arbiter that can be programmed to define the number of transactions a given port can transfer at a time, therefore allowing the other port access to memory. It also helps maximize core processor performance by allowing the core to preempt an active transaction from the internal bus port so the core is not starved. To further provide higher core to memory performance, a 32-bit memory region can be defined in bank 0 to eliminate ECC Read-Modify-Write operations on 4-byte writes (matches Intel XScale data size). This 32-bit region is ideal for core-related data structures, like DMA/AAU descriptors or I/O controller descriptors and control blocks.
The Intel IOP331 also has made significant improvements to the interrupt controller in order to reduce interrupt latency. The interrupt controller includes an advanced vector generator for both FIQ and IRQ interrupts, delivering the vector directly to the interrupt service routine, saving software overhead. Also included is an interrupt prioritizer that uses a two-bit field for each interrupt source to provide four levels of interrupt priority.
High integration provides board space and system-level cost savings
The integrated 133 MHz PCI-X to PCI-X bridge reduces system BOM cost and real estate. The integrated bridge includes 8 Kbyte data buffers in each direction and eliminates the need for an external PCI-X to PCI-X bridge providing a great deal of board space savings. The IOP331 is designed with a single ATU interface on the secondary PCI bus. This greatly simplifies code porting from designs using an external bridge as the programming and data-flow model are the same. The IOP331 provides central resource functionality on the secondary PCI-X bus and includes an integrated arbiter, clock outs for up to four devices and the capability to enable internal pull-up resistors on all the secondary PCI-X bus signals by a reset strap. The secondary PCI-X bus also supports public and private devices. A group of ten secondary IDSELs can be made public to the host or private to IOP331 by a reset strap. The bridge supports different PCI/PCI-X bus speeds and bus widths on the primary and secondary busses. For example, the primary bus can operate at PCI-66, while the secondary bus operates at PCI-X100. The IOP331 integrates a 2-channel DMA controller with support for unaligned transfers using both scatter-gather and direct modes. The 2-channel DMA controller facilitates increased PCI-to-memory throughput and memory-to-memory throughput. The IOP331 also integrates two UARTs, and two I2C ports to further reduce system cost/complexity. The 4-pin UARTs are 16550 register compatible with 64-byte transmit and receive FIFOs, and a programmable baud rate generator (up to 115 Kbps). If UART functionality is not needed, the eight pins used by the UARTs can also be used as GPIOs or external interrupts.
The Intel IOP331 provides an 8-bit or 16-bit, 66 MHz Peripheral Bus Interface (PBI) that is excellent for embedded applications requiring a connection to non-PCI peripheral components such as ASICs, flash memory, or DSPs. The PBI provides two chip selects and supports programmable bus width and wait states for two memory windows.
The IOP331 integrates two application acceleration engines targeted at specific applications: RAID5 XOR and iSCSI CRC32C. The Application Accelerator Unit (AAU) contains a hardware-based XOR capability using a 1 Kbyte queue to accelerate RAID-related parity calculations. The AAU speeds the transfer of read and write data to the memory controller and computes data parity across local memory blocks. The two DMA channels provide a hardware assist for iSCSI applications by calculating CRC32C on the data during the block transfer. The CRC engine uses the CRC32C algorithm required by the iSCSI specification. These application acceleration engines provide a significant performance boost, and eliminate the need for external ASICs saving cost and board space for RAID, Storage, and iSCSI networking applications. For more information see the product brief.
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