| Up to 800 MHz CPU, Integrated PCI Express* to PCI-X Bridge and High-Bandwidth Memory Controller Deliver Superior Performance |
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The IntelŽ IOP332 is a highly integrated I/O system on a chip for RAID on Motherboard and I/O-intensive storage, networking and communications applications. The IOP332 features an 800 MHz CPU, high-performance internal bus, enhanced memory controller, high-bandwidth PCI Express* to PCI-X* Bridge, and an improved interrupt controller to provide a high-performance, highly integrated processor solution. Target applications include RAID on Motherboard and PCI Express host-based adapters (RAID cards, iSCSI cards, FC cards, Security SSL NICs, etc.), and a host of other intelligent I/O applications that require a highly integrated, high-performance system on a chip processor with an integrated PCI Express interface.
As Intel's next-generation I/O processor, the IOP332 continues to build on Intel's strength in delivering high-performance, low-power Intel XScaleŽ microarchitecture processors. It integrates Intel® Super-Pipelined RISC Technology with a 7-stage integer/8-stage memory superpipelined core, 32 Kbyte data and instruction caches and operates up to 800 MHz. The IOP332 is code compatible with previous-generation Intel XScale microarchitecture processors such as the IntelŽ IOP321 I/O processor and other ARM*-based devices, simplifying code porting from existing designs. It is compliant with the ARM v5TE instruction set (excluding the floating point instructions). The internal bus operates at 266 MHz and offers internal bandwidth of up to 2.1 GB/sec.
The IOP332 provides ultra-fast memory transactions due to its DDR SDRAM enhanced memory controller and supports up to 2 GB of DDR 333 MHz memory or 1 GB of DDR2-400 MHz memory. Registered and unbuffered DDR 333 and registered DDR2-400 DIMMs can be used with the IOP332. The memory controller supports 32-bit or 64-bit memory subsystems with or without ECC. The IOP332 features a new enhanced memory controller that provides a direct port from the CPU to memory (core port) as well as a port from the ATU/internal bus to memory (internal bus port). This allows CPU memory accesses and data movement to and from the internal bus to occur providing high overall system performance. Performance optimizations can be made by programming the memory controller arbiter to define the number of transactions a given port can transfer at a time, therefore allowing the other port access to memory. It also helps maximize processor performance by allowing the core to preempt an active transaction from the internal bus port so the core is not waiting on a memory access. To provide higher core to memory performance, a 32-bit memory region can be defined in bank 0 to eliminate ECC Read-Modify-Write operations on 4-byte writes (which matches the Intel XScale microarchitecture data size). This 32-bit region is ideal for core-related data structures, like DMA/AAU descriptors or I/O controller descriptors and control blocks.
The IOP332 also has made significant improvements to the interrupt controller to help reduce interrupt latency. The interrupt controller includes an advanced vector generator for both FIQ and IRQ interrupts, delivering the vector directly to the interrupt service routine, which saves software overhead. Also included, is an interrupt prioritizer that uses a two-bit field for each interrupt source to provide four levels of interrupt priority. For more information see the product brief.
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