(#3134) Changes in ASM-51 and PL/M-51 PDF and DCL Files For 8xC51FC and 8xC51FB Microcontrollers
The latest releases of ASM-51 and PL/M-51 contain register definition files requiring alteration to correct errors regarding 8xC51FC registers. In addition, a new register present in the latest stepping of the 8xC51FB component needs defining.
Processor specific register definition files have the naming convention of RG51Fx.PDF for ASM-51 and RG51Fx.DCL for PL/M-51.
Starting with the RG51FC PDF and DCL files, note that the following registers and bit definitions are not implemented and should be removed:
RG51FC.PDF
RG51FC.DCL
AUXR DATA 08EH
AUXR BYTE AT(08EH) REG
INTENBH DATA 0A7H
INTENBH BYTE AT(0A7H) REG
INTENBL DATA 0A8H
INTENBL BYTE AT(0A8H) REG
INTPRIH1 DATA 0B5H
INTPRIH1 BYTE AT(0B5H) REG
INTPRIH0 DATA 0B6H
INTPRIH0 BYTE AT(0B6H) REG
INTPRIL1 DATA 0B7H
INTPRIL1 BYTE AT(0B7H) REG
INTPRIL0 DATA 0B8H
INTPRIL0 BYTE AT(0B8H) REG
INTPEND1 DATA 0C5H
INTPEND1 BYTE AT(0C5H) REG
INTPEND2 DATA 0C6H
INTPEND2 BYTE AT(0C6H) REG
IL6 BIT 0AEH IL6
BIT AT(0AEH) REG
IL5 BIT 0ADH IL5
BIT AT(0ADH) REG
IL4 BIT 0ACH IL4
BIT AT(0ACH) REG
Instead, the following registers and bits should be present:
RG51FC.PDF
RG51FC.DCL
IE DATA 0A8H
IE BYTE AT(0A8H) REG
IPH DATA 0B7H
IPH BYTE AT(0B7H) REG
IP DATA 0B8H
IP BYTE AT(0B8H) REG
EC BIT 0AEH
EC BIT AT(0AEH) REG
ET2 BIT 0ADH
ET2 BIT AT(0ADH) REG
ES BIT 0ACH
ES BIT AT(0ACH) REG
PPC BIT 0BEH
PPC BIT AT(0BEH) REG
PT2 BIT 0BDH
PT2 BIT AT(0BDH) REG
PS BIT 0BCH
PS BIT AT(0BCH) REG
PT1 BIT 0BBH
PT1 BIT AT(0BBH) REG
PX1 BIT 0BAH
PX1 BIT AT(0BAH) REG
PT0 BIT 0B9H
PT0 BIT AT(0B9H) REG
PX0 BIT 0B8H
PX0 BIT AT(0B8H) REG
.LM .00"
The easiest way to implement the needed changes is as follows:
For ASM-51, simply copy the RG51FA.PDF file to the RG51FC.PDF file (overwrite existing RG51FC.PDF file). Then insert the following somewhere in the DATA declaration section of the new RG51FC.PDF file and save:
IPH DATA 0B7H
For PL/M-51, copy the RG51FA.DCL file to the RG51FC.DCL file (overwrite existing RG51FC.DCL file). Then insert the following somewhere in the middle of the BYTE declaration section of the new RG51FC.DCL file and save:
IPH BYTE AT(0B7H) REG,
New RG51FB PDF and DCL files
The 8xC51FB devices have been stepped from A to B. With the exception of internal ROM size, the new B stepping is made with a "FX" core, making the peripheral features of the 8x3C51FB identical to that of the 8xC51FC. For this reason, the RG51FB.PDF (DCL) file now matches the RG51FC.PDF (DCL) file. This means that the following register should be present in the RG51FB files:
RG51FB.PDF RG51FB.DCL
IPH DATA 0B7H IPH BYTE AT(0B7H) REG
If your design uses the B stepping of the 8xC51FB, then simply copy RG51FC.PDF over the RG51FB.PDF file and RG51FC.DCL over the RG51FB.DCL file.
The new main features of the 87C51FB/83C51FB B-stepping are as follows:
4 Interrupt Priority Levels
Timer 2 Clock Out
Asynchronous Port Reset
64-Byte Encryption Array
3 Program Lock Bits
3 Signature Bytes
8xC51FB devices are recognized by an "A" suffix to the "FBO" number which is located on line 2 (underneath the device ID) on the top side of the component.
NOTE:
Due to changes in the encryption array, signature bytes, lock bits, number of required programming pulses (reduced to 5 from 25), and a new control pin (P3.3) for the 87C51FB step A devices, different programming algorithms are
required. Please consult your EPROM programmer manufacturer for software updates if necessary.
Future releases of ASM-51 and PL/M-51 will contain updated versions of all register definition files. Current DOS versions are as follows:
