40 MHz operation
Clock doubler
2 MBytes of linear address space
4 KBytes of RAM
Register to register architecture
Chip select unit with 3-chip select pins
Dynamic demultiplexed/multiplexed address/data bus per chip select
Programmable wait states per chip select
17 High speed capture/compare channels
8 High speed output compare channels
4 Flexible 16-bit timer/counters
8 PWM units with 8-bit resolution
2 Full duplex serial ports
Full duplex synchronous serial port
Stack overflow/underflow monitor
Serial debug unit
16 channel auto-scanning analog to digital converter
160Ld QFP package
Commercial temperature: 0C° to 70C° Ambient |
2X performance of current C196 products
Reduces external noise
More space for high level language compilation
Provides on-chip boot memory
More variable storage in fast on-chip memory
High performance and fast context switching
Glueless memory interfacing
Flexible bus interface
Eliminates need for external wait state generator
Very flexible I/O subsystem
Useful for time-base conversions
Versatile timer/counter structure
No CPU overhead for PWM generation
High speed, flexible synchronous communications
Hardware fault protection
Reading and writing of code RAM without CPU. Can set one hardware breakpoint
Reduces CPU overhead to control analog to digital converter |