| PCI/PCI-X Features |
| PCI revision 2.2 at 32/64 bit, 33/66 MHz |
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Application flexibility in LOM, embedded, or NIC use |
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64-bit addressing for systems with more than 4GB of physical memory |
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| PCI-X, rev.1.0a compliant host interface at clock rates up to 133 MHz |
Optimized server bus performance |
| Algorithms that optimally use advanced PCI MWI, MRM, MRL and PCI-X MRD, MRB, and MWB commands |
Efficient bus operations |
| Network Interface (MAC) |
| Low latency transmit and receive queues |
Network packets handled without waiting or buffer overflow |
| TBI interface, in addition to internal PHY, for IEEE 802.3z full duplex operation with SERDES |
Single device to interface with fiber or CAT-5 twisted pair transmission mediums |
| IEEE 802.3x compliant flow control support with software controllable pause times and threshold values |
Control over the transmission of Pause frames through software or hardware triggering |
| Internal Transceiver (PHY) Features |
| Integrated PHY for 10/100/1000 Mb/s full and half duplex operation |
Reduced board space and lower power dissipation compared to multi-chip MAC/PHY solutions |
| IEEE 802.3ab Auto-Negotiation |
Automatic link configuration including speed, duplex, and flow control |
| Proven PHY compatible with IEEE 802.3ab |
Robust operation over the installed base of CAT-5 twisted pair cabling |
| State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and cross-talk cancellation |
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Robust performance in noisy environments |
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Tolerance of common electrical signal impairments |
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| Host Offloading Features |
| RX and TX IP and TCP/UDP checksum off-loading capabilities |
Reduced host CPU utilization |
| Transmit TCP segmentation offloads host by sending up to 64K of block TCP data to network controller |
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Increased throughput and lower CPU utilization |
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Compatible with large send offload feature found in Windows* XP |
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| Advanced packet filtering |
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16 exact matched (unicast or multicast) |
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4096-bit hash filter for multicast frames |
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Promiscuous (unicast/multicast) transfer mode |
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Optional filtering of erred frames |
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| IEEE 802.1Q VLAN support |
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VLAN tag insertion and stripping |
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Packet filtering for up to 4096 VLAN tags |
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| Descriptor ring management hardware for TX and RX |
Optimized fetching and write-back mechanisms for efficient system memory and PCI banwidth usage |
| 16 KB jumbo frame support |
High throughput for large data transfers on compatible network segments |
| Interrupt coalescing (more than one packet per interrupt) |
Reduced interrupts generated by RX and TX operations, increasing throughput |
| Memory |
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Programmable host memory receive buffers (256B to 16KB) |
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Programmable cache line size from 16B to 256B |
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Efficient usage of PCI banwidth |
| 128-bit internal data path architecture |
Superior DMA transfer rate performance |
| Independent transmit and receive queues |
Enables simultaneous access by multiple CPUs |
| 64KB of configurable RX and TX Packet FIFOs |
No external FIFO memory requirements |
| Management Features |
| SDG3.0, WfM 2.0, PC2001 Compliance |
Remote network management capabilities via DMI 2.0 and SNMP software |
| Pre-boot eXecution Environment (PXE) Flash interface support |
Local flash interface for a PXE image |
| ACPI, PCI Power Management, Version 1.1 compliance |
PCI power management capability requirements for NIC and LOM applications |
| SNMP and RMON statistic counters |
Ease of monitoring system status |
| Wake on LAN* support |
Packet recognition and wakeup for NIC and LOM applications without software configuration |
| Additional Items |
| Six activity and link indication outputs that directly drive LEDs |
Indications for Link, RX, TX, and 10, 100, 1000 Mb/s |
| PHY detects polarity, MDI-X, and cable lengths. Auto MDI, MDI-X at all speeds |
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Easier network installation and maintenance |
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No need to know the difference between crossover and non-crossover cables |
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End to end wiring tolerance |
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| Internal PLL for clock generation using a 25 MHz crystal or a 25 MHz oscillator |
Lower component count and cost |
| JTAG (IEEE 1149.1) Test Access Port built in |
Simplified testing using boundary scan |
82544
The Intel® 82544EI and 82544GC Gigabit Ethernet Controllers are integrated, third-generation, Ethernet-LAN components, capable of supporting 1000 Mb/s, 100 Mb/s, and 10 Mb/s data rates. These single-chip devices manage both the MAC and PHY layer functions, and are optimized for LAN on Motherboard (LOM) designs, enterprise networking, and Internet appliances that use the Peripheral Component Interconnect (PCI) or PCI-X bus. The controllers provide a direct 32/64 bit, 33/66 MHz interface to the PCI bus that supports the PCI Local Bus Specification (revision 2.2), as well as the emerging PCI-X extension to the PCI Local Bus (revision 1.0a) at clock rates up to 133 MHz.
