| 8 integrated programmable microengines with 4K instruction program stores |
Enhanced second-generation flexible multi-threaded RISC processors that can be programmed to deliver intelligent transmit and receive processing, with robust software development environment for rapid product development |
Integrated Intel XScale Core
- 32 Kbyte – Instruction cache
- 32 Kbyte – Data cache
- 2 Kbyte – Mini-data cache
|
Embedded 32-bit RISC core for high performance processing of complex algorithms, route table maintenance and system-level management functions. Lowers system cost and saves board space |
| 2 unidirectional 32-bit media interfaces (Rx and Tx) programmable to be SPI-3, UTOPIA 1/2/3 or CSIX-L1. Each path is configurable for 4x8-bit, 2x16bit, 1x32bit or combinations of 8 & 16 bit data paths. |
Supports industry standard cell and packet Interfaces to media and fabric devices delivering 4 Gbps performance rates that can support OC-48 plus fabric encapsulation overhead or 4 x GbE; simplifies design and interface to custom ASIC devices |
| 1 industry-standard DDR DRAM interface |
Memory subsystem supports the network processor store-and-forward processing model |
| 2 industry-standard QDR SRAM interface |
Memory subsystem for look-up tables and access lists, or co-processors (such as CAM/TCAM, IPsec devices). NPF standardized interface for co-processors |
| PCI 2.2 64 bit/66 MHz I/O Interface |
Supports industry-standard connection to system host processors |
| Asynchronous control interface supports 8, 16 or 32 bit slow port devices |
Provides control interface for connecting to maintenance port of PHY devices and flash memory |
| Hardware support for memory access queuing |
Simplifies product development and reduces system cost |
| JTAG support |
Improve hardware debug ability |
| Software SDK |
Improves time to market via robust hardware and software development tools |
| Hardware Development Platform |
Improves time to market via robust hardware and software development tools |
Additional integrated hardware features:
- Hardware Hash Unit
(48, 64 and
128 bit)
- 16 KByte Scratchpad Memory
- Serial UART port for debug
- 4 general-purpose I/O pins
- 4 32-bit timers
|
Simplifies development, reduces development cost and saves board space |
Intel's second-generation network processors are the first implementation of Intel's Hyper Task Chaining technology. This unique network processing approach allows a single stream packet/cell processing problem to be decomposed into multiple, sequential tasks that can be easily linked together. The hardware design uses fast and flexible sharing of data and event signals among threads and microengines to manage data-dependent operations among multiple parallel processing stages with low latency. Through this combination of flexible software pipelining and fast inter-process communication, Hyper Task Chaining delivers rich processing capability at OC-48/2.5 Gbps line rates.
