|
|
|
 |
|
 | |
 |
Which type of SDRAM clock buffer should I use with the 440MX chipset?
Zero delay clock buffers have internal PLLs which cause contention with the PLL internal to the 440MX chipset. This contention can be observed in the form of jitter on the 440MX chipset DCLKO and DCLK (feedback) signals. Another observable symptom will be system lockup after the processor attempts to fetch the first 8 bytes of BIOS. The customer should use a SDRAM clock buffer that does not have an internal PLL. See the 440MX chipset design guide for examples.
Are 256Mbit SDRAMs supported?
The 440MX chipset does not support 256Mbit technology SDRAM.
128Mbit technology is supported. The 440MX chipset supports 2 slots of memory, 128MBytes in each slot, thus allowing for a total of 256MBytes of SDRAM.
There are SODIMM manufacturers building 256MByte SODIMMs using 128Mbit technology SDRAM. However, Intel has not validated these devices.
Where can BGA packaging information be found?
The 440MX chipset uses a 492-ball PBGA package. Further requirements for the 492 PBGA packaging can be found in Chapter 14 of the Intel Packaging Handbook.
Where can the register description for the 440MX chipset be found?
It is not in the datasheet. Please contact your Intel Field Sales Representative for this information.
Does the 440MX chipset support JTAG Boundary Scan testability?
No, the 440MX chipset does not support JTAG boundary scan testability. However, the 440MX chipset does support NAND tree testing. Please contact your Intel Field Sales Representative for details.
How should pin MA8# be strapped?
The proper strapping is to pull this signal down to Ground. Since there is an internal Pull-down on this signal, an external pull-down resistor is not required.
Which company produces the Intel SpeedStep® Technology Control Logic (ISSCL) described in the 440MX chipset design guide?
Intel SpeedStep® Technology and ISSCL are not supported by the Embedded Intel Architecture group.
What are the options for 440MX chipset BIOS development?
BIOS vendors such as General Software*, AMI*, and Phoenix Technologies* provide BIOS solutions for the 440MX chipset platform.
Where can schematics be found for a 440MX chipset reference design and are they available in Orcad Capture* format?
Schematics for the 440MX chipset platform can be found in the 440MX chipset design guide.
If USB is not required, how is this feature disabled?
In order to disable USB, the following steps must be taken:
1. OC[1:0]#: 10K Pull Up to 3.3V (one pull up for each signal)
2. USBP[1:0]+/-: 15K Pull Down to GND (one pull down for each signal)
3. CLK48: Direct Connect to GND.
4. VccUSB: Connect to 3.3V
How can Flash be used in an Embedded System?
For implementing flash memory on the PCI bus, please refer to AP-758 Flash Memory PCI Add-In Card for Embedded Systems. The Flash Memory PCI Add-In Card for Embedded Systems Schematics and Software Files is also available. |
|
|
|
Intel® 440MX Chipset