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What is the Intel® 80310 Processor Chipset?
The term 'Intel 80310 Processor Chipset' refers to the combination of the Intel® 80200 Processor based on Intel XScale® and the Intel® 80312 I/O Companion Chip.
Can I use the Intel 80200 Processor based on Intel XScale without Intel 80312 I/O Companion Chip?
Yes, you can. You will need to implement a memory controller, however. Intel offers an application note on an FPGA solution that explains how to accomplish this found here. A hardware example of this implementation is the Intel 80200 Processor Evaluation Platform Board (80200EVB) available from ADI. More information is located here.
When will the max Icc values of the Intel 80200 Processor be published in the datasheet?
A new revision of the Intel 80200 Processor Datasheet (order 273414-003) has been released and is located here. This new update contains the max Icc values.
All our PCI devices are 64-bit, do we need pull-ups on the secondary PCI expansion signals?
The secondary PCI bus may only have 64-bit devices connected to it, but you can't prevent 32-bit transactions from happening. Configuration cycles, I/O cycles and non-prefetchable memory all use 32-bit transactions. The PCI v2.2 Spec states in section 3.8, "The bandwidth requirements for I/O and configuration commands cannot justify the added complexity and, therefore, only memory transactions support 64-bit data transfers." Since 32-bit transactions cannot be avoided, we suggest using the pull-ups. For more information on the PCI Spec Version 2.2 please see PCISIG.
My design does not support battery back-up for SDRAM. What recommendations should I follow?
Applications that do not support battery back-up for SDRAM should follow these recommendations:
- Pull the PWRDELAY pin low through a 1.5K pull-down resistor. When the PWRDELAY is pulled low, the power fail state machine in reset, therefore this will not allow the power fail sequence to ever occur.
- Pull the CKE pins high on the SDRAMs, and leave the SCKE signals on the 80312 as 'no-connects'. This keeps the SDRAM from entering a self-refresh mode, which could cause a lock-up condition on the SDRAM device.
How do I use direct addressing on the Secondary of on the Intel 80310 Processor Chipset? It looks as if the Flash bank1 overlaps that address space.
Initially, the Flash bank does overlap the ATU Outbound Direct Addressing Window because the Initialization Boot Code must reside at 00000000H. However, after boot up, the software can move the flash bank to another address location and enable the ATU Outbound Direct Addressing Window.
In our design, there is no host. We are using the primary PCI Bus of the Intel 80310 Processor Chipset for expansion purposes only. How do we configure and initialize our primary PCI devices?
You can use the Intel 80310 Processor Chipset without an IA Host providing you take care of the following:
- You are required to implement PCI Arbitration on the primary PCI Side. There is not a PCI arbiter on the primary PCI interface.
- You must properly terminate the secondary PCI bus, even if it is not used.
- You are required to implement a PCI Clock on the primary PCI side.
- PCI Reset needs to be provided to the primary PCI side.
- Extra firmware for the Intel 80200 Processor is required to perform the PCI configuration on the primary PCI side, which an IA Host would have done. POCCAR and POCCDR registers are used to generate configuration cycles. You can pass this configuration cycle to the primary side via the Primary Address translation Unit to configure the PCI bus.
Is there another way to use the Intel 80310 Processor Chipset without an IA Host?
Yes, another option is to use the secondary PCI bus of the Intel® 80312 I/O Companion Chip only, instead of the primary PCI bus. With this configuration, you would not need an external arbiter on the secondary side because the secondary PCI bus has one integrated into it. Even though the primary PCI bus is not being used, you still must properly terminate the primary PCI bus.
Does the Intel 80312 I/O Companion Chip support Private PCI devices?
The Intel 80312 I/O Companion Chip does support "Private PCI Devices." According to section 1.3.3 of the Intel 80312 I/O Companion Chip Developer's Manual, under the title Private PCI Device Support, it states, "A key Intel 80312 I/O companion chip feature is that it explicitly supports private PCI devices on the secondary PCI bus without being detected by PCI configuration software. The bridge and Address Translation Unit work together to hide private devices from PCI configuration cycles and allow these devices to use a private PCI address space. The Address Translation Unit uses normal PCI configuration cycles to configure these devices."
Is the PCI bridge of the Intel 80312 I/O Companion Chip transparent or non-transparent?
It is both. The Intel 80312 I/O Companion Chip Developer's Manual alludes to the fact that the bus is non-transparent because it supports private addressing on the secondary side. If you do not implement private addressing, then the bus is transparent.
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Intel® 80310 Processor Chipsets (80312 & 80200)