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Can I use a 1:1 transformer in the receive side?
The LXT384/6 recommended receive configuration includes a 2:1 step-down transformer. The step-down effect prevents voltages in excess of 3.3V from being coupled into the LXT384/6 receiver. This can be an issue especially in T1 applications where the output voltage generated to drive long cable lengths may induce voltages in excess of 3.3V to the receiver.
In some systems however, legacy line interface modules might include 1:1 transformers. In these cases, switching to a 2:1 receive transformer may not be practical. The receive circuit in the following picture presents a solution for those situations:
How do I tri-state the LXT384/6 output drivers?
The output driver tri-state capability is useful in designing protection systems without external relays. The LXT384/6 offer three distinct methods for tri-stating the output drivers.
- The first method consists in holding TCLK Low for the corresponding channel. This method allows driver tri-stating on a per-channel basis.
- The second method consists in setting the OE pin low. This action tri-states all the output drivers. The OE pin in the LXT384/6 allows fast switching between redundant and the working boards without having to individually tri-state every output driver.
- The third method is to use the Output Enable Register (OER) in software control mode. Setting a bit to &1& in the OER, tri-states the output driver of the corresponding transceiver.
For details on implementing redundancy applications without relays please refer to Application Note AN119.
How can I get Quality and Reliability information for T1/E1 components?
Q&R information is not readily available on the Web site for the TAO communications products and should be requested through the support channels. These Reliability reports contain information such as Solder Reflow, Metal Stress, Thermal Shock, FITs, MTBFs, etc. Customers are also requesting the "Gate Count" of a part, which is Intel proprietary information that should only be given out on a per customer basis, and should be cleared through Intel Corporation Legal, Q&R and the Product Manager.
What is the difference between Unipolar and Bipolar mode operation?
Bipolar and unipolar modes are two different ways for an LIU to interface to a framer or back end ASIC. The following is from the receive perspective. The transmit perspective is similar. The T1 or E1 data (zeros and ones) is coded as alternate positive and negative pulses for signaling logic 1's on the line. Zeros are coded as a zero voltage. In bipolar mode, two data lines, (RPOS and RNEG) plus a clock line (RCLK) connect the LIU to the framer. A logic "1" on RPOS tells the framer that a positive pulse was detected on the line. A logic "1" on RNEG tells the framer that a negative pulse was detected on the line. In bipolar mode, it's the framer's responsibility to decode the sequence of positive and negative pulses into a sequence of logic zeros and ones. This is done by the AMI or B8ZS/HDB3 decoders inside the framer. In unipolar mode, only one data line (RDATA) plus a clock (RCLK) connect the LIU to the framer. The sequence of positive and negative pulses is decoded inside the LIU. The resulting sequence of zeros and ones is output on TDATA. In unipolar mode, the AMI or B8ZS/HDB3 decoders are automatically enabled inside the LIU.
How can I use the Analog JTAG port to test my metallic Tx/Rx interfaces on the LXT384?
The AT1 and AT1 pins are the analog test port input and output respectively. A voltage can be forced into any of the TTIP or RTIP pins. The voltage at the corresponding TRING or RRING pin is output at AT2. The selection is made by setting the ASR register in the JTAG interface.
If the connections across the primary transformer windings are good, there should be a total impedance of approximately 2KW (DC) in the receive path (2x 1 KW). The transmit impedance will be equal to approximately two times the transmit resistor value. As an example, for E1 the impedance across the transmit path will be approximately 22W (2 x 11 W). If the impedance is much higher than the expected value, there might be an open circuit in the path (possibly caused by a bad component or soldering issue). As you can see, this feature allows testing the analog interface connections. This is something that is not possible with conventional (digital) JTAG interfaces.
How should I adjust the 560pF capacitor in the transmit interface?
The main purpose of the transmit 560pF capacitor is to slightly increase the high frequency transmit return loss. Typical applications already have a substantial amount of parasitic capacitance. Sources of parasitic capacitance are the protection elements, common mode chokes, long PCB traces and connectors. Too much capacitance might cause some slight ringing in the output pulse. In these cases, the designer is advised to reduce the 560pF capacitor. However, for most practical situations, a 560pF capacitor will provide good results.
What are the layout recommendations for the analog interface for the LXT384?
The following are the general guidelines for the T1/E1 interface layout
- Place decoupling capacitors very close to the corresponding TVCC/VCC pins.
- Avoid crossing transmit and receive signals to minimize cross-talk.
- Avoid routing digital signals near analog signals (TIP/RING) and receiver inputs.
- Provide ample power and ground planes.
- Route differential pairs like RTIP/RRING and TTIP/TRING close together. Make sure the trace length for differential signals is about the same.
- Don't extend the ground plane beyond the line side of the transmit and receive transformers. Ground plane noise could be coupled into the line signals increasing RF emissions.
- Minimize trace lengths connecting the LIU to transformers and connectors.
- When using surge protection elements in the line side of the transformer such as TVS, place them as close as possible to the disturbance source, i.e., the connector.
How do I interface the LXT384/6 with 5V logic?
The LXT384/6 is a 3.3V device including 5V tolerant inputs. Therefore, the device can interface directly with 5V TTL inputs and outputs without the need for level shifters. There is a difficulty when interfacing digital outputs to a CMOS device at 5V. Unfortunately a pullup won't work with the LXT384 because of ESD circuitry. If you can use the LXT380 (for E1 only), that part can directly drive 5V CMOS devices by making VCCIO equal to 5V. With the LXT384 use a level-shifter such as a FET, a BJT, a Phillips 74LVT04 that can have the outputs forced to 5.0 V with a pull-up even if VCC is 3.3 V, a 74LVC4245 dual Vcc level shifter, or a 74LS06 with open-collector outputs.
What is the maximum jitter allowed on MCLK?
MCLK is used internally as a reference for the clock recovery and jitter attenuation DPLLs. We strongly recommend a jitter free, independent MCLK clock from a crystal oscillator. Any jitter on MCLK will be added to the RCLK output transparently. The designer should decide the maximum output jitter that can be tolerated at the output given the specifications the equipment should comply with. In addition, since MCLK is used in the clock recovery PLLs, occasional jitter hits may induce bit errors.
What is the maximum TCLK gap width the LXT384/6 can tolerate?
In multiplexer applications TCLK may be gapped due to stuffing and de-stuffing. The LXT384/6 jitter attenuator includes a FIFO that can accommodate a gapped TCLK. The limiting factor for the maximum gap width is the FIFO length. Due to the FIFO control logic implementation, the maximum gap width in UI is limited to:
- 64 bit FIFO : 56 UI
- 32 bit FIFO : 24 UI
Exceeding these values will cause FIFO overflow or underflow. As an example, if the LXT384/6 is operating in E1 mode, the TCLK average frequency will be 2.048 MHz. If the FIFO is set to 64 bit, the maximum gap width is:
- Tgap £ 56 * (1 / 2.048 ' 10^6 ) = 27.3 ms
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Intel® LXT384/6