Chapter 1 - So you got your first IXP12xx, now what?
Overview of book.

Chapter 2 - The IXP12xx programming environment
This chapter provides the necessary background on the IXP12xx hardware and software tools needed to program the microengines of the IXP12xx. The IXP12xx hardware, as it relates to programming the IXP12xx, is detailed, including a "day in the life of a packet" example that covers how a packet enters, is processed by, and finally leaves the IXP12xx. From the software perspective, and overview of the various IXP12xx tools and programming environments are covered including the Developer's Workbench and the IXA SDK. Read this chapter

Chapter 3 - "Hello World" for the microengines
This chapter provides a step-by-step guide to writing, compiling, and running a simple IXP12xx microengine program using the Developer's Workbench. This chapter starts with installation of the Developer's Workbench and ends with a working IXP12xx microengine program.

Chapter 4 - Microblock design philosophy
This chapter provides an overview of the various microengine software design approaches. The chapter motivates and explains the microblock design philosophy that serves as the basis for the rest of the code in the book.

Chapter 5 - Receiving and processing basics
This chapter provides an explanation of the packet reception process on the IXP12xx. This chapter concludes with working, single-threaded microengine code to receive and count packets.

Chapter 6 - Intra-microengine programming concepts
This chapter extends the single-threaded concepts of Chapter 5 to the multithreaded environment within a single microengine. Intra-microengine synchronization and communication mechanisms like the microengine's thread arbiter and absolute registers are used to make the packet counting example code execute faster.

Chapter 7 - Inter-microengine programming concepts
This chapter continues the extension of the packet counting example into the area of multiple microengines. Various inter-microengine synchronization and communication primitives like atomic memory operations, SRAM CAM locks and inter-thread signals are experimented with to see how they affect the overall performance of the packet counting code.

Chapter 8 - Fast data structure processing
This chapter covers the architectural features of the IXP12xx that impact data structure organization and algorithm design. Memory latency hiding techniques, pipelining, parallelism and memory alignment issues are covered. To illustrate these concepts, Ethernet bridging code is developed using these techniques and the hash unit of the IXP12xx.

Chapter 9 - Transmitting data
This chapter provides the details of the transmit state machine on the IXP12xx, culminating with code to transmit packets out of the IXP12xx. With this transmit code, and the code from Chapters 7, 8, this chapter concludes with an integrated example of packet reception, Ethernet bridging and packet transmission.

Chapter 10 - Advanced programming topics
This chapter covers four topics: * Receiving packets from MAC fast ports. Certain high-speed IXP12xx ports, called fast ports, require new receive code to efficiently deal with their high data rates. * Transmitting packets on multiple ports of different speeds. Due to the design of the transmit state machine, dealing with ports of different speeds on the IXP12xx requires some special code to prevent slower ports from affecting faster ports * Programming the ready-bus sequencer. * Using the Cyclic Redundancy Check (CRC) feature of the IXP1240 and IXP1250.

Chapter 11 - Writing microACEs
This chapter explains what a microACE is, why you would want to build one, and how to go about building one. In this chapter the Ethernet bridging code from Chapter 9 is turned into a microACE.

Chapter 12 - Tips and tricks
This chapter provides a list of the tips and tricks for programming, debugging, and optimizing code on the microengines.

Chapter 13 - Next Generation IXP Hardware and Software
This chapter provides a sneak preview of the next generation of IXP network processors, code-named Sausalito and Castine. Both the new hardware features of Sausalito and Castine as well as enhancements to the microblock programming model are covered.