|
Chapter 2, Page 24.
There should be a third bullet point in front of the third paragraph under "The Ready-Bus Sequencer."
Chapter 5, Page 77-78.
Indentation is off for most of the code listing. The code on the CD-ROM has the proper indentation.
Chapter 5, Page 80.
In the description of lines 53-61, the text reads: "The get_buffer_data_ptr call..." but should read "The buffer_get_data_ptr call..." The code correctly references the function named buffer_get_data_ptr.
Chapter 5, Page 81.
In the section describing lines 69-75, the section is referring to lines 81-85, not 69-75.
Chapter 5, Page 87, Figure 5.8.
The figure has labels "Before Pop" and "After Pop," but these should be "Before Push" and "After Push," respectively.
Chapter 6, Page 107, fourth paragraph.
"WAITING | PENDING == WAITING" should be "WAITING & PENDING == WAITING"
Chapter 6, Page 117, first paragraph.
"Here discarding a packet means unlocking the receive state by clearing the valid bit..." should be "Here discarding a packet means unlocking the receive state by setting the valid bit..."
Chapter 6, Page 125, third paragraph, first sentence.
"before the ready-bus sequencer has a chance poll the MAC" should be "before the ready-bus sequencer has a chance to poll the MAC"
Chapter 6, Page 125, last paragraph, last sentence.
"can be slowed down with either with dummy spin loops" should be "can be slowed down with either dummy spin loops"
Customer Tip for chapter 7 Arthur Berkowitz notes: The SRAM unit contains a read lock order (RLK) configuration bit that controls the behavior of the SRAM CAM locks. "If set, when a read_lock command is placed into the read_lock fail queue, all subsequent read_lock commands are placed into the read_lock fail queue regardless of whether or not the memory address is entered in the read_lock CAM. This ensures that all read_lock commands are serviced in the order in which they were issued."
As a practical note, the BSP configuration for VxWorks that ships with IXA SDK 2.0, sets the RLK bit by default.
Chapter 7, Page 132.
The code as shown will not compile with the latest version of the microC compiler (available on IXA SDK 2.01). The problem is on line 54, a write-only transfer register is being read. The solution is to first write the data into a general-purpose register and then move the value into the write-only transfer register. To do this, add the following definition at line 48:
rcv_state_fields_t gpr_mask;
Then replace lines 53 and 54 with:
gpr_mask.whole = 0;
gpr_mask.parts.valid = 1;
mask = gpr_mask;
Please replace the files of the same name in the Chapter 7 sub-directory of the CD-ROM.
Chapter 7, Page 136, second title.
"12-127" should be "125-127"
Chapter 7, Page 136, last paragraph.
The last paragraph of the section describing lines 53-62 of this example states:
"Why not simply use the r_state and r_handle variables?"
However, this is no r_handle variable in the code. Instead, the r_handle reference should have been rcv_state->handle, and thus the sentence should read:
"Why not simply use the r_state and rcv_state->handle variables?"
Chapter 7, Page 138, first title.
"Lines 6-7, 11, 32-33" should be "Lines 6-7, 10, 27-28"
Chapter 7, Page 138, second title.
"Lines 20-22" should be "Lines 18-20"
Chapter 7, Page 138, second title.
"Lines 24-29" should be "Lines 21-26"
Chapter 7, Page 142.
The caption to Figure 7.4 contains a typo. The word "Rrunning" should be "Running."
Chapter 7, Page 151 and Figure 7.7 on page 152.
All references to thread 3 and thread 4 should be changed to thread 2 and thread 3.
Chapter 7, Page 152 and Figure 7.7 on page 152.
"that is both easy read and write" should be "that is both easy to read and write"
The sample code for Chapters 8 and 9 do not compile properly with the microengine C compilers that come with IXA SDK 2.01 and IXA SDK 2.01a. If you are using either of these SDK releases, replace the source code from the CD-ROM with the files in this ZIP file.
Chapter 7, Page 156, Line 10 of the sample code.
The comment on this line is:
/* Wait to be told to run /
During formatting, the closing comment symbol in the code (*/) was replaced with a bold /. Thus, the line should read:
/* Wait to be told to run */
The code on the CD-ROM should be correct.
Chapter 7, Page 157, Section titled "Lines 23-24, 33-342, 46-47"
The section heading has a typo. The number 342 should be 34.
Chapter 7, Page 159, Figure 7.8
Figure 7.8 does not contain the result of the benchmark for the inter-thread signal mechanism with the receive reassembly state stored in scratchpad memory.
The CD-ROM contains the data collected for this experiment (and a graph containing the results). Also, Figure 10.4 has the interthread signal scratchpad results.
Chapter 9, Pages 167, 169, and 170.
The transmit code supplied in Chapter 9 does not properly handle packets larger than 64 bytes. You must make two corrections.
- Lines 169 and 170 should read:
port_state.current_data_ptr =
(void*)((unsigned int)(port_state.current_data_ptr) + (64 / sizeof(long long)));
instead of:
port_state.current_data_ptr =
(void*)((unsigned int)(port_state.current_data_ptr) + 64);
This correction accounts for the quad-word addressing of SDRAM on the IXP1200.
- Add the following line after line 167:
mpacket->eop = 0;
This addition ensures the per-mpacket state maintained by the fill threads gets properly initialized for each new packet.
Page 182, first paragraph, first sentence.
The first sentence of the section titled "Parallelism" reads:
"Notice on lines 32-37, and again on lines 71-76, that..."
The referenced line numbers are incorrect. The sentence should read:
"Notice on lines 48-53, and again on lines 87-92, that..."
Chapter 10, Page 219.
The paragraph directly below Figure 10.1 incorrectly states that the IX bus mpacket transfer time is 1000 nanoseconds. This should be only 100 nanoseconds. Consequently, it is possible for the IX bus to keep up with the inter-mpacket arrival rate of gigabit Ethernet MAC device, assuming no other traffic is utilizing the IX bus.
Chapter 11
tells you how to write microACEs, providing code examples written using microC. Since the publishing of the book, Intel has decided not to release support for microACEs written in microC in any IXA SDK 2.x release. Writing microACEs in microengine assembly is still supported however, and all of the concepts described in Chapter 11 still apply to writing microACEs in microengine assembly. In order to run the microACE sample from the book, the microACE example from Chapter 11 was rewritten in microengine assembly. To run the sample, please put the following two files in the microblock directory and use them instead of the microC files.
File #1 File #2
Chapter 13, Figure 13-3, Page 295.
The first list should have been labeled FULL_ELEMENT_LIST as shown in this corrected diagram (instead of RX_THREAD_FREELIST)
| 
