Intel® PCI Bridges

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This document provides information on the Intel® 41210 Bridge, including a functional overview, mechanical data, package signal location and bus functional waveforms.

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The Intel® 41210 Serial to Parallel PCI Bridge evaluation board is a PCI-Express enabling tool with PCI-X expansion slots that are used to evaluate the operation of the 41210 Bridge.

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This document provides layout information and guidelines for designing platform or add-in board applications with the Intel(R) 41210 Serial-to-Parallel PCI Bridge.

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The Intel® 41210 Serial to Parallel PCI Bridge (also called the 41210 Bridge or the 41210) integrates two PCI Express-to-PCI/PCI-X bridges. Each bridge follows the PCI-to-PCI Bridge programming model. The PCI Express port is compatible with the PCI Express Specification, Revision 1.0a. The two PCI bus interfaces are comparable with the PCI Local Bus Specification, Revision 2.3 and the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.

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Designed specifically for Host Bus Adapters (HBAs) and add-in cards, the Intel® 41210 Serial to Parallel PCI Transparent Bridge chip connects parallel bus PCI and PCI-X technology-based peripheral card applications directly to the newest generation of high-speed PCI Express* serial I/O architecture-enabled system platforms.

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This document provides information on the Intel® 41110 Bridge, including a functional overview, mechanical data, package signal location and bus functional waveforms.

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This document provides layout information and guidelines for designing platform or add-in board applications with the Intel® 41110 Serial-to-Parallel PCI Bridge.

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The Intel® 41110 Serial to Parallel PCI Bridge (also called the 41110 Bridge or the 41110) integrates two PCI Express-to-PCI/PCI-X bridges. Each bridge follows the PCI-to-PCI Bridge programming model. The PCI Express port is compatible with the PCI Express Specification, Revision 1.0a. The two PCI bus interfaces are comparable with the PCI Local Bus Specification, Revision 2.3 and the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.

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Conceived as a low-cost bridge chip solution for connecting legacy PCI* and PCI-X* devices to new generation PCI Express* serial interconnect host systems, the Intel® 41110 Serial to Parallel PCI transparent bridge chip is ideal for quick time-to-market (TTM) porting of existing or new PCI and PCI-X add-in card layout designs to PCI Express cards compatible with PCIe host system slots.

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The Intel® 31154 133 MHz PCI Bridge is Intel's fourth generation PCI Bridge and it implements a number of new features designed to provide superior performance and functionality in both PCI and PCI-X environments. This application note describes the implementation and usage of a unique, new feature, the Alternative ID register field, otherwise known as the "Masquerade Feature" of the Intel® 31154 133 MHz PCI Bridge.

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This document describes both hardware and software issues that should be considered when migrating from the IBM* PCI-X to PCI-X Bridge to the Intel® 31154 133 MHz PCI Bridge.

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This document highlights design considerations you must review prior to manufacturing an adapter card or motherboard that implements the Intel(R) 31154 133 MHz Bridge

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This application note describes the Intel® Boundary Scan Description Language (BSDL) syntax, semantics, and hardware test validation and results on a 31154 133MHz PCI Bridge.

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This document provides information on the Intel(R) 31154 133 MHz PCI Bridge, including a functional overview, mechanical data, package signal location and bus functional waveforms.

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This document provides layout information and guidelines for designing platform or add-in board applications with the Intel(R) 31154 133 MHz PCI Bridge.

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The 31154 Bridge is a PCI expansion board that is used to evaluate the operation of the 31154 Bridge.

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The Intel(R) 31154 133MHz PCI Bridge is a PCI component that functions as a highly concurrent, low latency transparent bridge between two PCI busses. The 31154 133MHz PCI Bridge is capable of operating as a PCI-to-PCI bridge in the configurations.

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The Intel® 31154 133 MHz PCI Bridge with opaque mode provides vendors of OEM systems, add-in cards and embedded applications with a high-performance, feature-rich 4th-generation PCI bridging device.

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Specification Update for the Intel® 31154 133 MHz PCI Bridge

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This document defines the differences between the 21555AA/BA bridge when compared with the 21555AB/BB bridge. The 21555 bridge is a second generation Non-Transparent PCI-to-PCI bridge.

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This application note explains the steps required to reset, initialize, and configure the 21555 Non-Transparent PCI-to-PCI bridge (referred to as the 21555) such that it can forward memory transactions upstream and downstream through designated address windows.

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This document discusses the features that the users should consider when adapting a 21555 into a design for a 21554. By installing a 21555 in place of a 21554, the design team can utilize several new features that are described in this document. Look for the "New Feature" marking in the margins of the document or in tables to see the advantages of the 21555.

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This document explains how to optimize performance when forwarding memory transactions across the 21555 non-transparent PCI-to-PCI bridge.

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This document describes how the 21555 resolves issues concerning the use of PCI add-in cards where the processor on the PCI add-in card is used as a system slot or host processor. It also describes 21555 issues and design considerations when the same add-in card is used as a peripheral master or as a local processor add-in card. This dual capability means that two separate add-in card design and development efforts are not needed to support system and peripheral slot add-in cards.

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The 21555 supports the attachment of standard parallel 8-bit Flash ROM. The PCI expansion ROM base address register (BAR), at offset 30h, is offered with ROM sizes ranging between 4KB and 16MB. If required, this feature can provide the PCI expansion ROM interface for the subsystem. If the subsystem does not need this capability, the PCI expansion ROM BAR can be disabled by clearing bit 0 of this register.

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This document presents guidelines for hardware implementation of the 21555 PCI-to-PCI Bridge chip for non-transparent applications (21555) in a system. This application note is limited to hardware implementation of the 21555 only and does not cover the specific application of any devices that are part of the local subsystem, or any initialization code needed to configure the 21555 or an associated intelligent subsystem.

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This application note describes the serial ROM hardware setup and explains the preload sequence of the serial ROM. Example code for programming the serial ROM through command and status register (CSR) access is provided. A description of the VPD operation is also provided.

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This datasheet describes the 21555, which is a PCI peripheral device that performs PCI bridging functions for embedded and intelligent I/O applications. This datasheet contains overview information that is subject to change with steppings.

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This document describes the 21555 PCI-to-PCI Bridge Evaluation Board (also referred to as the DE1B55503). The DE1B55503 is an evaluation and development board for systems based on the 21555 Non-Transparent PCI-to-PCI Bridge chip (the 21555). For detailed information about the 21555, refer to the 21555 Non-Transparent PCI-to-PCI Bridge Data Sheet.

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Intel's 21555 is a PCI peripheral device that performs PCI bridging functions for embedded and intelligent I/O applications. The 21555 has a 64-bit primary interface, a 64-bit secondary interface, and 66-MHz capability. A related PCI peripheral device, referenced for comparison purposes, has a 64-bit primary interface, a 64-bit secondary interface, and 33-MHz capability. The 21555 is a ?non-transparent? PCI-to-PCI bridge that acts as a gateway to an intelligent subsystem. Unlike a transparent PCI-to-PCI bridge, the 21555 is specifically designed to bridge between two processor domains. Notice: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.

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The Intel® 21555 Non-Transparent PCI-to-PCI bridge chip enables add-in card vendors to deliver high-performance, intelligent option cards and embedded products that previously were not possible. Designed specifically for applications where a processor is used behind a PCI-to-PCI bridge, the 21555 provides a clean architecture for creating a product with multiple processor domains.

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Specification Update for the 21555 Non-Transparent PCI-to-PCI Bridge.

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This application note describes the configuration of the 21154 PCI-to-PCI Bridge (21154) in a system. This application note is limited to the PCI configuration of the 21154 only and does not cover any hardware application topics, or describe the details of the PCI protocol.

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This document presents guidelines for hardware implementation of the 21154 PCI-to-PCI Bridge chip (21154) in a system. This application note is limited to hardware implementation of the 21154 only and does not cover any devices that might be behind the 21154 or any initialization code needed to configure the 21154 chip. This application note includes implementation notes on layout, clocking, secondary bus IDSEL mapping, interrupt routing, and secondary bus arbitration. Implementation on both a motherboard and an option card is covered. For most situations, hardware implementation issues are the same. In addition, guidelines for interrupt routing on option cards are provided in the interrupt discussion.

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This document describes the differences between the 21154AC when compared to the 21154AE and the 21154BC when compared to the 21154BE.

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The 21154 is a second-generation PCI-to-PCI bridge that is fully compliant with the PCI Local Bus Specification, Revision 2.1 and the Advanced Configuration Power Interface (ACPI) Specification. The 21154 has a 64-bit primary bus interface and a 64-bit secondary bus interface. The 64-bit interfaces interoperate transparently with either 64-bit or 32-bit devices. The 21154 provides full support for delayed transactions, which enables the buffering of memory read, I/O, and configuration transactions.

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The 21154 is a second-generation PCI-to-PCI bridge and is fully compliant with PCI Local Bus Specification, Revision 2.3. The 21154 has a 64-bit primary bus interface and a 64-bit secondary interface. The 64-bit interfaces interoperate transparently with either 64-bit or 32-bit devices. The 21154 provides full support for delayed transactions, which enables the buffering of memory read, I/O, and configuration transactions. The 21154 has separate posted write, read data, and delayed transaction queues with the most buffering capability of all Intel's 2115x PCI-to-PCI bridge products. In addition, the 21154 supports buffering of simultaneous multiple posted write and delayed transactions in both directions. Among the features provided by the 21154 are: a programmable 2-level secondary bus arbiter, an IEEE standard 1149.1 JTAG interface, live insertion support, a 4-pin general-purpose I/O interface, individual secondary clock disables, and enhanced address decoding. The 21154 has sufficient clock and arbitration pins to support nine PCI bus master devices directly on its secondary interface.

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This document describes the 21154 PCI-to-PCI Bridge Evaluation Board (also referred to as the EB154). The EB154 is an evaluation and development board for systems based on the 21154 PCI-to-PCI Bridge chip (the 21154). The 21154 is a second-generation PCI-to-PCI bridge and is fully compliant with the electrical and protocol requirements of the PCI Local Bus Specification, Revision 2.2, and the PCI-to-PCI Bridge Architecture Specification, Revision 1.0. The 21154 provides full support for delayed transactions, which enables the buffering of memory read, I/O, and configuration transactions. The 21154 has separate posted write, read data, and delayed transaction queues with significantly more buffering capability than first-generation bridges.

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This application note describes the configuration of the 21152 PCI-to-PCI bridge chip in a system. This application note is limited to the PCI configuration of the 21152 only and does not cover any hardware application topics, or describe the details of the PCI protocol.

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This document presents guidelines for hardware implementation of the 21152 PCI-to-PCI Bridge chip (21152) in a system. This application note is limited to hardware implementation of the 21152 only and does not cover any devices that might be behind the 21152 or any initialization code needed to configure the 21152 chip. This application note includes implementation notes on layout, clocking, secondary bus IDSEL mapping, interrupt routing, and secondary bus arbitration. Implementation on both a motherboard and an option card is covered. For most situations, hardware implementation issues are the same. In addition, guidelines for interrupt routing on option cards are provided in the interrupt discussion.

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As of July, 1996, Intel’s Computing Enhancement Group has consolidated available historical device and documentation errata into this new document type called the Specification Update. We have endeavored to include all documented errata in the consolidation process, however, we make no representations or warranties concerning the completeness of the Specification Update. This document is an update to the specifications contained in the Affected Documents/Related Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also contain information that was not previously published.

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This application note describes the differences between the 21152AB and the S21152BB.

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Intel's second-generation 21152 PCI-to-PCI Bridge is fully compliant with PCI Local Bus Specification, Revision 2.3. The 21152 is pin-to-pin compatible with Intel's 21052, which is fully compliant with PCI Local Bus Specification, Revision 2.0. The 21152 provides full support for delayed transactions, which enables the buffering of memory read, I/O, and configuration transactions.

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The 21152 is a second-generation PCI-to-PCI bridge and is fully compliant with PCI Local Bus Specification, Revision 2.3. The 21152 provides full support for delayed transactions, enabling buffering of memory read, I/O, and configuration transactions. The 21152 has separate posted write, read data, and delayed transaction queues with significantly more buffering capability than first-generation bridges. In addition, the 21152 supports bi-directional buffering of simultaneous multiple posted write and delayed transactions. Among the features provided by the 21152 are a programmable 2-level secondary bus arbiter, individual secondary clock software control, and enhanced address decoding. The 21152 has sufficient clock and arbitration pins to support four PCI bus master devices directly on its secondary interface. The 21152 allows the two PCI buses to operate concurrently. This means that a master and a target on the same PCI bus can communicate while the other PCI bus is busy. This traffic isolation may increase system performance in applications such as multimedia.

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This document describes the Intel® 21152 PCI-to-PCI Bridge Evaluation Board (also referred to as the EB152). The EB152 is an evaluation and development board for systems based on the Intel® 21152 PCI-to-PCI Bridge chip (the 21152). Intel's 21152 is a second-generation PCI-to-PCI bridge and is fully compliant with the electrical and protocol requirements of the PCI-to-PCI Bridge Architecture Specification, Revision 2.1, and the PCI-to-PCI Bridge Architecture Specification, Revision 1.0. The 21152 provides full support for delayed transactions, which enables the buffering of memory read, I/O, and configuration transactions. The 21152 has separate posted write, read data, and delayed transaction queues with significantly more buffering capability than first-generation bridges. For detailed information about the 21152, refer to the 21152 PCI-to-PCI Bridge Data Sheet.

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This white paper focuses on the industry's transition to PCI Express desktop and server systems with an emphasis on storage. It offers some insight into the revolutionary performance advantages, features and scalability PCI Express serial I/O architecture provides over traditional PCI parallel bus technology, platforms and devices. It will also look at a new PCI Express to PCI-X bridge chip that will provide Time-to-Market (TTM) features and technology enabling for PCI Express platforms.

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