| Features |
Benefits |
| Balanced chipset architecture |
Delivers optimal system performance through well-aligned bandwidths (system bus, memory, SP and I/O bandwidths are well balanced). |
| 400 MHz, 128-bit system bus capability |
6.4 GB/s system bus supports up to four Intel® Itanium® processors per node for optimal system performance. |
| High memory capacity |
The DDR Memory Hub (DMH) provides a maximum of 8 DIMM slots with an aggregate of 32 memory slots enabled per processor node. Maximum capacity supported per processor node is 128 GB using 4 GB DIMMs. |
| Two high bandwidth scalability ports per SNC and SIOH |
Provides sufficient system headroom for single-node or multiple-node and degraded configurations. |
| Four hub interface 2.0 connectivity |
Delivers 1 GB/s bandwidth per connection, providing multiple I/O configuration options and offering both flexibility and performance. |
| I/O pre-fetch engine and built-in cache |
Delivers full bandwidth on data return. |
| High performance PCI/PCI-X bridge support |
Provides support to all PCI/PCI-X I/O devices, from legacy PCI to higher performance PCI-X at 133 MHz. |
| Advanced platform RASUM |
Features such as hot-plug modules for processor and memory, Error Correction Code (ECC) protection and correction, memory scrubbing, Memory Device Failure Recovery (MDFR), multiple redundant I/O paths and error logging combine to yield a more reliable platform, reducing downtime for repair and ensuring data integrity across all interconnects and busses. |
