Intel® E7501 ChipsetOverview
The second in a family of volume server chipsets, the Intel® E7501 chipset supports dual-processor (DP) server systems optimized for the Intel® Xeon® processor. The Intel E7501 chipset design delivers maximized system bus, memory and I/O bandwidth to enhance performance, scalability and end-user productivity while providing a smooth transition to next-generation server technologies.
Platform Features that Maximize Performance
Dual Intel® Xeon® processors with a 533 MHz system bus provide up to 4.3 GB/s of available bandwidth.
Dual DDR-266 memory channels operate in lock-step to provide up to 4.3 GB/s of memory bandwidth.
Three hub interface 2.0 connections provide multiple high-bandwidth I/O configuration options, yielding up to 3.2 GB/s of I/O bandwidth.
Product information
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Download product brief
The Intel® E7501 chipset represents the next step in Intel®-based server chipset technology. The Intel E7501 chipset supports dual-processor server systems optimized for the Intel® Xeon® processor with 533 MHz system bus and Intel NetBurst® microarchitecture. The Intel E7501 chipset design delivers maximized system bus, memory, and I/O bandwidth to enhance performance, scalability, and end-user productivity while providing a smooth transition to the next-generation server technologies.
File Type/Size: PDF 335KB
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Features and benefits
| Supports 2 Intel® Xeon® processors with 512 KB L2 cache for dual-processing server systems | Delivers a platform that brings Intel NetBurst® microarchitecture and the Hyper-Threading Technology◊ of the Intel® Xeon® processor to deliver best-in-class performance for peak server workloads. |
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| 533 MHz system bus capability | Supports a high-performance platform by enabling a 4.3 GB/s system bus bandwidth that can support greater memory and I/O bandwidths. |
| Intel® Hub Architecture 2.0 connection to the MCH | This point-to-point connection between the MCH and the 3 Intel® 82870P2 controller hub devices provides greater than 1 GB/s of bandwidth. Error Correction Code (ECC) protection, coupled with high data transfer rates, support I/O segments with greater reliability and faster access to high-speed networks. |
| Intel® 82870P2 controller hub | Introduces next-generation PCI/PCI-X performance and significantly enhances platform flexibility. Two independent 64-bit, 133 MHz PCI-X segments and 2 hot-plug controllers (1 per segment) for each Intel 82870P2 controller hub device allow up to 6 PCI-X buses per system. |
| Dual-channel DDR-266 memory interface | Offers a maximum memory bandwidth of 4.3 GB/s through a 144-bit wide, 266 MHz Double Data Rate ( DDR) SDRAM memory interface with densities up to 512 megabits. |
| Advanced platform RASUM | Provides a more reliable platform with features such as memory Error Correction Code (ECC) with Intel® x4 Single Device Data Correction1, hardware memory scrubbing, MCH SMBus target interface, hub interface ECC, and the availability of enhanced error status information maintained through reset. |
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Packaging information
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The Intel® E7501 Chipset Memory Controller Hub (MCH)
The Intel® E7501 chipset is targeted for the server market, both front-end & general purpose low- to mid-range. It is intended to be used with the Intel® Xeon® processors with 512-KB L2 cache & 533 MHz system bus. The chipset consists of three major components: Intel® E7501 Chipset MCH, ICH3-S, & the PCI/PCI-X 64-bit Hub 2.0 (P64H2). The MCH provides the processor system bus interface, memory controller, hub interface for legacy I/O, & three high performance hub interfaces for PCI/PCI-X. File Type/Size: PDF 2341KB |
1005-pin Flip Chip-Ball Grid Array (FC-BGA) |
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Intel® 82801CA Integrated Controller Hub
This document -- Intel® 82870P2 PCI/PCI-X 64-bit Hub 2 (P64H2) Datasheet -- describes the basic features, modes and registers supported by the P64H2, as well as signal descriptions and electrical and mechanical specifications. File Type/Size: PDF 1610KB |
421-pin Ball Grid Array (BGA) |
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Intel® 82870P2 64-bit PCI/PCI-X controller
This document, the Intel® 82801CA I/O Controller Hub 3 (ICH3-S) Datasheet, describes the basic features, modes and registers supported by the ICH3-S, as well as signal descriptions and electrical and mechanical specifications. File Type/Size: PDF 2193KB |
567-pin Flip Chip-Ball Grid Array (FC-BGA) |
- Product and Performance Data
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◊ Intel® Hyper-Threading Technology (Intel® HT Technology) requires a computer system with an Intel® processor supporting Intel HT Technology and an Intel HT Technology enabled chipset, BIOS, and operating system. Performance will vary depending on the specific hardware and software you use. See www.intel.com/products/ht/hyperthreading_more.htm for more information including details on which processors support Intel HT Technology.
1 In a x4 DDR memory device, the Intel® x4 Single Device Data Correction (Intel® x4 SDDC), provides error detection and correction for 1, 2, 3, or 4 data bits within that single device and provides error detection, up to 8 data bits, within two devices.