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What are the IA-32 processor targeting options in the 10.x compilers? There are two types of processor-specific optimization options:
- Processor-specific options of the form /Qx<code> (-x<code> on Linux*) generate specialized and optimized code for processors specified by the code. The resulting executables from these processor-specific options can only be run on the specified or later Intel® processors, as they incorporate optimizations specific to those processors and use a specific version of the Streaming SIMD Extensions (SSE) instruction set. A run-time check is inserted in the resulting executable that will halt the application if run on an incompatible processor. This is intended to help you quickly find out that the program was not intended for the processor it is running on and potentially avoids executing an illegal instruction.
- Processor-dispatch options of the form /Qax<code> (-ax<code> on Linux*) allows the generation of multiple code paths. Processor dispatch technology provides a check at execution time to determine which processor the application is running on and use the best code path which is compatible with that processor.
Where the value for <code> can be:
| S |
May generate Intel® SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel® processors. Optimizes for the 45nm Hi-k next generation Intel® Core™ microarchitecture. Performs optimizations not enabled with processor value O. |
| T |
May generate Intel® SSSE3, SSE3, SSE2, and SSE instructions for Intel® processors. Optimizes for Intel® Core™ microarchitecture. Performs optimizations not enabled with processor value O. |
| P |
May generate Intel® SSE3, SSE2, and SSE instructions for Intel processors. Optimizes for enhanced Pentium M processor microarchitecture and Intel® Netburst™ microarchitecture. Performs optimizations not enabled with processor value O. |
| O |
May generate Intel® SSE3, SSE2, and SSE instructions. Optimizes for the enhanced Pentium M processor microarchitecture and Intel® Netburst microarchitecture. Code path may execute on Intel and non-Intel processors that support Intel® SSE3 such as some AMD* processors. It should be noted that for this processor value there is no -axO nor /QaxO option. |
| N |
May generate Intel® SSE2 and SSE instructions for Intel® processors. Optimizes for Intel® Netburst microarchitecture. Performs optimizations not enabled with processor value W. |
| W |
May generate Intel® SSE2 and SSE instructions. Optimizes for the Intel® Netburst microarchitecture. Code path may execute on Intel® and non-Intel® processors that support Intel® SSE2 such as some AMD processors. |
| K |
May generate Intel® SSE instructions. Optimizes for the Pentium® III processor and Intel® Pentium® III Xeon® processor. Code path may execute on Intel® and non-Intel® processors that support Intel® SSE such as some AMD processors. |
Which processor-specific option is best for my processor?
| S |
Quad-Core Intel® Xeon 54XX, 33XX series Dual-Core Intel® Xeon 52XX, 31XX series Intel® Core™ 2 Extreme 9XXX series Intel® Core™ 2 Quad 9XXX series Intel® Core™ 2 Duo 8XXX series Intel® Core™ 2 Duo E7200 |
| T |
Quad-Core Intel® Xeon® 73XX, 53XX, 32XX series Dual-Core Intel® Xeon® 72XX, 53XX, 51XX, 30XX series Intel® Core™ 2 Extreme 7XXX, 6XXX series Intel® Core™ 2 Quad 6XXX series Intel® Core™ 2 Duo 7XXX (except E7200), 6XXX, 5XXX, 4XXX series Intel® Core™ 2 Solo 2XXX series Intel® Pentium® dual-core processor E2XXX, T23XX series |
| P |
Dual-Core Intel® Xeon® 70XX, 71XX, 50XX Series Dual-Core Intel® Xeon® processor (ULV and LV) 1.66, 2.0, 2.16 Dual-Core Intel® Xeon® 2.8 Intel® Xeon® processors with SSE3 instruction set support Intel® Core™ Duo Intel® Core™ Solo Intel® Pentium® dual-core processor T21XX, T20XX series Intel® Pentium® processor Extreme Edition Intel® Pentium® D Intel® Pentium® 4 processors with SSE3 instruction set support |
| N (IA-32 only) |
Intel® Xeon® processors Intel® Pentium® 4 processors Intel® Pentium® M |
| K (IA-32 only) |
Intel® Pentium® III Xeon Intel® Pentium® III |
If you must also support non-Intel processors – then the best option to use is processor value O instead of P for processors that support the SSE3 instruction set or use W instead of N for processors that support the SSE2 instruction set.
Note: Processor values O and W do not enable some optimizations in the compiler that are enabled with processor values P and N. The processor values O, W, and K produce binaries that should run on non-Intel processors such as AMD processors, which implement the same capabilities as the corresponding Intel processors.
What set of processor-specific optimization options are recommended? Based on the capabilities of the installed hardware base and the advantages enabled by these options, the recommended option settings are:
/QaxT /QxW
This option combination will produce binaries with two code paths, using the process-dispatch technology described above. One code path will take full advantage of prcoessors based on Intel Core microarchitecture.
The other code path takes advantage of the capabilities provided by processors based on the Intel Pentium 4 and Xeon processors with SSE2 support and other compatible processors with SSE2 support.
Note: The resulting software will not run on systems which do not include the SSE2 instruction set, which includes the original Intel processors through the Intel Pentium III processor. SSE2 provides significant floating point optimization and reproducibility that is not available without SSE2.
Which processor is targeted by default?
- On IA-32 systems running Windows* and Linux*, no processor specific code is generated by the compiler. The resulting code path should run on any generic IA-32 processor.
- On Intel® 64 systems running Windows and Linux, /QxW or –xW is on by default. The compiler may generate SSE2 and SSE instructions. Optimizes for Intel® Netburst microarchitecture. The resulting binary should run on all Intel 64 compatible systems, including those produced by AMD.
- On IA-32 systems running the Mac OS* X, –xP is on by default. The compiler may generate SSE3, SSE2, and SSE instructions and the code is optimized for enhanced Pentium M processor microarchitecture.
- On Intel 64 systems running the Mac OS* X, -xT is on by default. The compiler may generate SSSE3, SSE3, SSE2, and SSE instructions and the code is optimized for the Intel® Core microarchitecture.
Other common questions:
This applies to:
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