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The document clarifies how the IERR# signal is deasserted on the Pentium® Pro processor bus.
Current documentation regarding the IERR# signal is unclear and needs further clarification. The quotes listed below leaves a customer wondering if the bit cannot be overwritten while it is asserted, how does software clear the IERR# signal from within a handler routine?
(1) From the Pentium Pro Family Developer's Manual, Volume 1: Specifications, section A.1.31 (Appendix A, pg. A-15): "...It keeps IERR# asserted until it is turned off as part of the Machine Check Error or the NMI handler in software..."
(2) From the Pentium® Pro Family Developer's Manual, Volume 3: Operating System Writer's Guide, section 16.6.3, (table 16.7, p. 16-13), the MCi_STATUS register for External Bus Error, bit 44, Other Information/IERR: "... While this bit is asserted, it cannot be overwritten."
The sentence referenced above in (1) is misleading and seems to imply that there is a bit somewhere in an MSR that can control the assertion or deassertion of the IERR# signal. This implication is misleading.
The bit referenced above in (2) does not control the IERR# signal. A closer look at the description of this signal states that this bit only tells you that a failure caused the IERR# signal to be asserted. It does not state that assertion of this bit causes IERR# to be asserted. The bit is only a flag telling you that IERR# WAS asserted.
IERR# is deasserted by an NMI software handler by having the handler RESET the processor. This can be done directly by the NMI handler or by having an SMI generated from the NMI and the SMI handler resetting the processor.
This applies to:
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