Intel's 45nm CMOS Technology

Foreword

• Foreword

  Bill Holt, Senior Vice President, General Manager, Technology and Manufacturing Group

    Podcast with Kaizad Mistry, VP Technology & Manufacturing Group, Intel

Current Articles

Transistors and Interconnects

• 45nm High-k+Metal Gate Strain-Enhanced Transistors

  In this paper, the authors detail the transistors used in Intel's 45nm technology node that feature Hi-k gate dielectrics and metal gates along with a third generation of strained silicon to achieve record NMOS and PMOS performance.

• Process and Electrical Results for the On-die Interconnect Stack for Intel's 45nm Process Generation

  Here, the authors explore the issues associated with on-die interconnects and describe how they are addressed on Intel's 45nm high-performance logic process technology. The combined MT1-MT9 interconnect stack provides high performance and high reliability, and enables a completely Pb-free product.

Variation and Design for Manufacturability

• Managing Process Variation in Intel's 45nm CMOS Technology

  The key message of this paper is that process variation is not an insurmountable barrier to Moore's Law. The authors use data from the 45nm process generation where process variation is shown to be at least equivalent to (and in many cases better than) process variation in the 65nm- and 90nm-process generations.

• 45nm SRAM Technology Development and Technology Lead Vehicle

  The authors look at the X-chip and its role in enabling process development for the 45nm node. The SRAM design challenges due to scaling and circuit innovations are discussed along with the advantages provided by Hi-K metal gate technology in achieving aggressive design goals.

• 45nm Design for Manufacturing

  Co-optimization between design and process has lead to changes in design rules for the last few process generations, especially changes in Poly, one of the most critical layers for control of variation. The variation, density, and yields on the 45nm process validate these Intel engineers' Design for Manufacturing methodology.

Packaging and Reliability

• 45nm Transistor Reliability

  The authors present an overview of the reliability of Intel's 45nm HK+MG transistors and demonstrate that these devices deliver reliability comparable to conventional SiO₂ devices at ~30% higher operating fields with negligible SILC degradation.

• Flip-Chip Packaging Technology for Enabling 45nm Products

  These authors showcase their solutions to the key challenges associated with the development of a high-volume manufacturing compatible assembly process for packaging Intel’s 45nm, completely Pb-free devices.

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