Tera-scale Computing

Runtime Environment for Tera-scale Platforms

Bratin Saha, Programming Systems Lab, CTG
Ali-Reza Adl-Tabatabai, Programming Systems Lab, CTG
Richard L. Hudson, Programming Systems Lab, CTG
Vijay Menon, Programming Systems Lab, CTG
Tatiana Shpeisman, Programming Systems Lab, CTG
Mohan Rajagopalan, Programming Systems Lab, CTG
Anwar Ghuloum, Programming Systems Lab, CTG
Eric Sprangle, Visual Computing Group, DEG
Anwar Rohillah, Visual Computing Group, DEG
Doug Carmean, Visual Computing Group, DEG

Index words: runtime environment, scalable user level services, tera-scale platform

Citation for this paper: Saha, B.; Adl-Tabatabai, A.; Hudson, R.; Menon, V.; Shpeisman, T.; Rajagopalan, M.; Ghuloum, A.; Sprangle, E.; Rohillah, A.; Carmean, D. "Runtime Environment for Tera-scale Platforms." Intel Technology Journal. http://www.intel.com/technology/itj/2007/
v11i3/4-environment/1-abstract.htm (August 2007).

ABSTRACT

This paper presents the design and implementation of a runtime environment for tera-scale platforms. System software stacks currently view tera-scale platforms as an "SMP (symmetric multiprocessor) on a die." We show that there are fundamental differences between tera-scale and SMP systems that require that the software (SW) stack be re-architected. In particular, the SW stack needs to provide (1) support for efficient fine-grain parallelism, (2) programmability enhancements such as transactional memory, and (3) support for heterogeneous platforms and applications.

We discuss the design and implementation of a Many-Core RunTime (McRT) environment—a prototype tera-scale runtime environment—and show how it addresses the challenges of a tera-scale runtime. We also present simulation results from a tera-scale simulator to show that McRT enables excellent scalability on tera-scale platforms.

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