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Tera-scale Computing
FOREWORD
Sean Koehl, Technology Strategist, Intel Corporate Technology Group
Jerry Bautista, Director of Technology Management, CTG Microprocessor Technology Laboratory
Jim Held, Intel Fellow, Corporate Technology Group, Director, Tera-Scale Computing Research, Intel Corporation
Ram Huggahalli, Principal Engineer/Network Platform Architect, CTG Communication Technology Lab
The coming of the microprocessor in 1968 began a new age. With this tool we have vastly accelerated our ability to learn, design, and innovate. With each new silicon process generation, faster transistors and microarchitectural innovations have enabled computational power to grow dramatically, opening new possibilities and opportunities and moving from microprocessors as simple calculators to multi-media and communication devices, that connect us to a world-wide web filled with information, entertainment and a new kind of electronic community. Software execution sped up almost automatically as clock speeds increased and the world learned to purchase based on MHz, then GHz.
However, we have now reached a turning point, where we must rely more on another benefit of each new silicon process, the doubling of transistor count each generation known as Moore’s Law. To maintain the pace of increasing computational capability with the energy efficiency needed for mobility and within the power and thermal limits of large datacenters, we find ourselves as an industry turning from increased frequency to parallelism. The power efficiency inherent in dividing work among multiple processor cores on one die allows us to continue dramatic increases in performance. In the next decade or so, processors with not just two or four, but 10s or 100s of compute cores will be the norm with a commensurate increase in performance.
Aside from simply providing the same tera-scale computation at lower cost, these parallel microprocessors will surpass the massively parallel supercomputers of the past. Tera-bits of inter-processor I/O bandwidth, exceptionally low core-core latency, and a pool of integrated system resources will enable new applications that are hard to imagine today, just as the early PC user doing text-based word processing would be astounded by the digital content creation capabilities of today’s machines. We can see on the horizon a new class of model-based applications enabled by parallel computing. Computers will have the ability to form increasingly sophisticated digital “models” of things and ideas. This will give applications the ability to recognize, find, and even synthesize real or virtual people, places, and things amidst a sea of data. Computers’ ability to process and analyze data will reach a point where they may no longer be considered simple tools: they will act more as our trusted advisors and assistants – anticipating needs without being “asked.”
This is the motivation of Intel’s Tera-scale Computing Research program. In order to enter this new and challenging era of innovation, we must create new architectures, based on 10s or even 100s of cores. We must develop not just new hardware, but new system and application software to effectively manage and execute more and more threads at the same time. Alongside academia and our industry fellow travelers, we must challenge the previous way of doing things, while at the same time finding a smooth path to a new world of mainstream parallel computing. It is not overdramatic to say we are entering a renaissance in computing.
In this issue of the Intel Technology Journal, we share some of our most recent findings with you. The topics, ranging from hardware to software, represent a few key projects from the many underway at Intel. We hope that the results presented here not only assist in other research and development efforts, but that they inspire new projects and new ideas on parallel microprocessing. Our tera-scale computing vision is aggressive, with a potentially huge ROI; it will take thousands of minds to realize the future hundred-core chips with their billions of transistors.