Technology with the Environment in Mind

  Section 3 of 10  

Materials Technology for Environmentally Green Micro-electronic Packaging

PB-FREE INITIATIVE: FIRST LEVEL INTERCONNECT MATERIALS (FLI)

Intel recently announced the achievement of a significant milestone in the quest to deliver RoHS-compliant Pb-free FLI solutions in micro-electronic packaging. The transition to Pb-free FLI interconnects that connect the silicon die to the substrate eliminated the last 5% of Pb remaining in the package. Traditionally, tin-lead solder alloy has been used for FLI chip-to-substrate and 2LI substrate-to-board attachment interconnect materials. The presence of lead in tin-based solder alloys, mostly with the composition of eutectic 63Sn-37Pb, lends the solder superior thermal and mechanical characteristics for microelectronic assembly and reliability. However, the inherent toxicity of lead has raised serious environmental and public health concerns. Developing lead-free alternative solder alloys for micro-electronic substrates is of paramount importance. Intel selected tin-silver-copper (SAC) solder metallurgy as the lead-free chip attachment material for its 45nm CPU products. Compared to their tin-lead counterpart, high tin content, lead-free C4 solders possess physical properties less desirable for assembly and reliability: higher surface tension, increased mechanical stiffness, and a higher melting point. A number of technical challenges have been encountered and solved during Intel's lead-free C4 interconnect development. For example, reduced wettability of lead-free solder with die copper bumps can pose challenges to the downstream underfill process. Moreover, optimization of substrate solder metallurgy has also shown to be very effective in improving the mechanical robustness of the C4 interconnect, and in minimizing the occurrence of C4 brittle solder joints. The change to Pb-free SAC solder alloy necessitated the development of alternate flux materials to clean off the more tenacious tin oxides from the solder surface and form a robust FLI solder joint. The new flux material needed to be stable at high process temperatures as well as be cleanable following the chip attach process to allow strong adhesion between the underfill, the bump metallurgy, and the die passivation. The formation of a robust FLI, Pb-free joint significantly increased the current carrying capability of the joints. The transition to Pb-free FLI solder materials also necessitated the development of underfill materials technology designed to mitigate additional thermo-mechanical stresses imposed on the die due to stiffer FLI joints.

Changing from a Pb-based C4 substrate solder to a Pb-free metallurgy drove an increase in the peak reflow temperature during die attach in assembly requiring Pb-free-reflow-compliant substrate materials technology. The selection of the dielectric materials set (core material, buildup layer, and solder resist) in the Pb-free substrate was therefore critical to ensure robust reliability performance of the package at higher reflow temperatures. In particular, the glass transition temperature (Tg) and the coefficient of thermal expansion (CTE) values of the dielectric materials set were carefully selected to minimize the risk of substrate warpage, substrate dielectric material cracking, and die damage.

Thus, along with changing the solder alloy material to one that is Pb-free, a judicious choice of the associated materials sets allowed Intel to solve the challenge of removing the remaining 5% of lead, thereby achieving EU RoHS-compliant FLI packaging technology.

  Section 3 of 10  

Back to Top