Intel's 45nm CMOS Technology

45nm High-k+Metal Gate Strain-Enhanced Transistors

Chris Auth, Technology and Manufacturing Group, Intel Corporation
Mark Buehler, Technology and Manufacturing Group, Intel Corporation
Annalisa Cappellani, Technology and Manufacturing Group, Intel Corporation
Chi-hing Choi, Technology and Manufacturing Group, Intel Corporation
Gary Ding, Technology and Manufacturing Group, Intel Corporation
Weimin Han, Technology and Manufacturing Group, Intel Corporation
Subhash Joshi, Technology and Manufacturing Group, Intel Corporation
Brian McIntyre, Technology and Manufacturing Group, Intel Corporation
Matt Prince, Technology and Manufacturing Group, Intel Corporation
Pushkar Ranade, Technology and Manufacturing Group, Intel Corporation
Justin Sandford, Technology and Manufacturing Group, Intel Corporation
Christopher Thomas, Technology and Manufacturing Group, Intel Corporation

Index words: CMOS transistor, logic technology, high-k gate dielectric, metal gate

Citations for this paper: Auth, C.; Buehler, M.; Cappellani, A.; Choi, C.-H.; Ding, G.; Han, W.; Joshi, S.; McIntyre, B.; Prince, M.; Ranade, P.; Sandford, J.; Thomas, C. "45nm High-k+Metal Gate Strain-Enhanced Transistors." Intel Technology Journal. http://www.intel.com/technology/itj/2008/
v12i2/1-transistors/1-abstract.htm (June 2008).

ABSTRACT

For the 45nm technology node, high-k+metal gate transistors have been introduced for the first time in a high-volume manufacturing process [1]. The introduction of a high-k gate dielectric enabled a 0.7x reduction in Tox while reducing gate leakage 1000x for the PMOS and 25x for the NMOS transistors. Dual-band edge workfunction metal gates were introduced, eliminating polysilicon gate depletion and providing compatibility with the high-k gate dielectric.

In addition to the high-k+metal gate, the 35nm gate length CMOS transistors have been integrated with a third generation of strained silicon and have demonstrated the highest drive currents to date for both NMOS and PMOS. An SRAM cell size of 0.346µ² has been achieved while using 193nm dry lithography. High yield and reliability has been demonstrated on multiple single-, dual-, quad-, and six-core microprocessors.

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