Addressing the Challenges of Tera-scale Computing

A Programming Model for Heterogeneous Intel® x86 Platforms

Article Description

The client computing platform is moving towards a heterogeneous architecture that consists of a combination of cores focused on scalar performance, and of a set of throughput-oriented cores. The throughput-oriented cores (such as those in the Intel® microarchitecture codename Larrabee processor) may be connected over both coherent and non-coherent interconnects, and they may have different instruction set architectures (ISAs). This article describes a programming model for such heterogeneous platforms. We discuss the language constructs, runtime implementation, and the memory model for such a programming environment. We implemented this programming environment in an Intel x86 heterogeneous platform simulator and we ported a number of workloads to our programming environment. We present the performance of our programming environment on these workloads. (Filetype/Size: PDF 287 KB)

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