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Addressing the Challenges of Tera-scale Computing
Flexible and Adaptive On-chip Interconnect for Tera-scale Architectures
Article Description
In this article we present the design of an on-chip interconnect with aggressive latency, bandwidth, and energy characteristics that is also flexible and adaptive. We present the design choices and policies within the constraints of an on-chip interconnect and demonstrate the effectiveness of these choices for different usage scenarios. (Filetype/Size: PDF 415 KB)
