Addressing the Challenges of Tera-scale Computing

Ultra-low Voltage Technologies for Energy-efficient Special-purpose Hardware Accelerators

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This article describes ultra-low voltage design techniques and learnings from a video motion estimation engine fabricated in 65nm CMOS technology. This chip is targeted for special-purpose, on-die acceleration of sum of absolute difference (SAD) computation in real-time video encoding workloads on power-constrained mobile microprocessors. Various datapath circuit innovations within the accelerator improve energy efficiency for SAD calculations at nominal supplies, while ultra-low voltage optimizations enable robust circuit operation for further efficiency gains at ultra-low supply voltages, with minimal impact on nominal supply performance. Silicon measurements of the accelerator demonstrate performance of 2 GHz at the nominal supply voltage of 1.2 V, with scalable performance of up to 2.4 GHz at 1.4 V, 50°C. Robust, ultra-low voltage, optimized circuits enable operation measured down to 230 mV (sub-threshold). Across this wide range of operational supplies, maximum energy efficiency of 411 GOPS/W or 12.8 macro-block SADs/nJ is achieved by operating the accelerator at a near-threshold voltage of 320 mV, for 23 MHz frequency and 56 µW power consumption. This represents a 9.6X higher efficiency than at the nominal 1.2 V operation. (Filetype/Size: PDF 711 KB)

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