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Volume 12, Issue 02

Intel's 45nm CMOS Technology


Intel Technology Journal - Featuring Intel's recent research and development

ISSN 1535-864X DOI 10.1535/itj.1202

  • Volume 12
  • Issue 02
  • Published June 17, 2008
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Marian Lacey
melacey@pacbell.net

Marian Lacey is the Technical Writing Editor of the Intel Technology Journal. She was a scientific editor for the National Lab at Los Alamos, has run her own writing and editing business, and has been a training designer and technical writer and editor for Intel Corporation. As a member of Intel's Design Technology staff, she designed in-house training materials and wrote user manuals and tutorials for Intel's internal CAD tools. She taught a quarterly "Planning and Writing Technical Material" workshop at Intel University. She also taught English at the college level and was for many years a teacher of English as a Second Language. She holds a B.A. and an M.A. in English from the University of British Columbia.

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