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New Functionality Enabled
Speed-Path Design
We describe the design environment and the advantages of using it by looking at the speed-path design activity commonly performed in IC design. This design activity encompasses both circuit design and layout design. It uses several tools and various types of data in both of the design domains. The flow of this activity is shown in Figure 5.
Figure 5: Speed path optimization flow
Speed-path analysis and optimization flow start with the timing verification stage when a circuit designer receives timing constraints and budgeting. The designer runs tools to identify critical paths. To optimize the paths with violations, there are multiple possibilities:
- Increase the driver strength.
- Reduce the driver load.
- Optimize the interconnect loading.
The first two options are handled by the device-sizing functionality in circuit design, and the last one is carried out in layout design.
With current tools, all these activities (shown in Figure 5) are carried out by different tools. The data is exchanged by means of files and often there are multiple design engineers involved. Since data files are used, it is difficult to exchange partial data, i.e., complete design data is exchanged between the tools. By some estimates, it takes in the order of weeks to optimize a path if accurate interconnect loading is to be obtained. The reason for this is that layout design is carried out by a different person and the turn-around time for obtaining data is long. The most common reasons for the long turn-around time are that layout design has to be completed before data is obtained, and data interfacing is difficult. Thus, circuit designers tend to optimize the paths using device sizing and do not explore all possible solutions, such as optimizing the interconnect delay.
With the new integrated design environment, where all the different tools are accessible via a common user interface, the interconnects can be optimized as easily as devices can be sized. Also, since all the tools are working with the same data model, the data is exchanged in memory. This enables interactive design, which provides an improved turn-around time between various tools. Another advantage of the integrated design environment is that it provides the capability for incremental design. Only data that is modified by one tool needs to be addressed by other affected tools. With the integrated layout planner, a circuit designer is able to make changes to the block layout plan without involving a different person to do the layout design. Changes in interconnect parasitic values are updated in the common data model, and the timing analyzer is able to perform incremental analysis of the change.
Noise Handling
Another activity the new environment enables is the efficient handling of noise. It has become important to account for noise as the operating voltage for deep sub-micron design is decreasing, and the noise effect is becoming more visible. Noise analysis also involves information that is traditionally spread across both the circuit design and layout design stages. As both of these stages are tightly integrated in the new design flow, all the information required for noise analysis is available simultaneously.
Some of the noise analysis features made available have been adapted from published work [6].