A. Brand, California Technology and Manufacturing Group, Intel Corp.
A. Haranahalli, California Technology and Manufacturing Group, Intel Corp.
N. Hsieh, California Technology and Manufacturing Group, Intel Corp.
Y.C. Lin, California Technology and Manufacturing Group, Intel Corp.
G. Sery, California Technology and Manufacturing Group, Intel Corp.
N. Stenton, California Technology and Manufacturing Group, Intel Corp.
B.J. Woo, California Technology and Manufacturing Group, Intel Corp.
S. Ahmed, Portland Technology Development Group, Intel Corp.
M. Bohr, Portland Technology Development Group, Intel Corp.
S. Thompson, Portland Technology Development Group, Intel Corp.
S. Yang, Portland Technology Development Group, Intel Corp.

Index Words: CMOS, shrink, interconnect

Abstract

Process 856 is a 0.25um-generation logic technology currently in volume manufacturing, which has been optimized for high performance, yield, and density. This process is being used to manufacture high-performance products including the Intel® Celeron^TM and Pentium® II microprocessors. The process has a high equipment re-use rate to reduce cost. Using the older equipment has increased the challenge of scaling to smaller pitch, particularly in the interconnect process. Transistor optimization allows volume production of Pentium II microprocessors at 450 MHz. High yield has also been achieved, both before and after a 5% linear shrink of the initial 0.25um design rules.

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