Intel's 0.25 Micron, 2.0Volts Logic Process Technology

Intel's 0.25 Micron, 2.0Volts Logic Process Technology (continued)

Page 8 of 8

Authors' Biographies

Adam Brand
Adam Brand received his BSEE and his MSEE from the Massachusetts Institute of Technology in 1991. He joined Intel in 1991 and is currently working in the California Technology and Manufacturing 0.25um Device Group. His interests include transistor performance optimization, high voltage device development, and circuit modeling. His email address is adam.d.brand@intel.com.

Aravinda Haranahalli Aravinda Haranahalli
Aravinda Haranahalli received an MS in Physics in 1976 and a Ph.D in Materials Engineering 1980 from the University of Florida. He joined Intel in 1984 and has held various management positions in technology, manufacturing, and business development. He currently manages interconnect technology development for 0.2um. Before joining Intel he held technology positions at Texas Instruments and Fairchild. His current interests include technology, manufacturing, and business management. His email address is aravinda.r.haranahalli@intel.com.

Ning Hsieh Ning Hsieh
Ning Hsieh received a Ph.D. in Materials Science from Northwestern University in 1979. He worked for various semiconductor companies including IBM, Fairchild, and DEC. He joined Intel in 1993 and has worked in CTM Technology Development since then. His work experience is mostly in process integration. He has published six external papers and has six patents. His email address is ning.hsieh@intel.com.

Yi-Ching Lin Yi-Ching Lin
Yi-Ching Lin graduated from the University of California, Berkeley with a Ph.D. in EECS in 1981. Prior to joining Intel in 1987, he was with Texas Instruments and Monolithic Memories, Inc. He has been working in the area of process integration for microprocessor, Flash and EPROM memories. He had also worked on technology transfer from D2 to foreign foundries, including those located in Taiwan and Japan. His email address is yi-ching.lin@intel.com.

George E. Sery George E. Sery
George E. Sery is an Intel Fellow and director of Device Technology Optimization in Intel's California Technology and Manufacturing group. Mr. Sery is currently responsible for directing process characterization, performance improvement, and capability enhancement for Intel's 0.25 micron CMOS logic technology. He received a B.S. and M.S. in electrical engineering from the University of Minnesota in 1976 and 1978 respectively. He joined Intel in 1978 as part of the SRAM Technology Development group. He has been involved with the development of NMOS and CMOS technologies for logic, SRAM, and Flash memory applications. For each technology, he has led the device physics team responsible for device development and process characterization. His email address is george.sery@intel.com.

Nicky Stenton Nicky Stenton
Nicky Stenton received a M.S. in Materials Engineering from Lehigh University in 1982. She joined Intel in 1982 and most recently has been working on transistor process development in the California Technology and Manufacturing P856 Integration group. Her email address is nicky.stenton@intel.com.

Been-Jon Woo Been-Jon Woo
Been-Jon Woo received a B.S. in Chemical Engineering from the National Taiwan University in 1975 and a Ph.D. from USC in 1979. She joined Intel in 1984 after working at Fairchild. She has worked in EPROM, Flash, and logic technology integration in the California Technology and Manufacturing group. She is currently the 0.25um transistor integration manager. Her email address is been-jon.k.woo@intel.com.

Shahriar Ahmed Shahriar Ahmed
Shahriar Ahmed joined Intel in 1985, initially as an interconnect device engineer working on Process 448. He subsequently was part of the team that developed P648 and coordinated the final transfer to high-volume manufacturing. Shahriar then moved on to be the device engineer for Intel's first bi-CMOS process. His next project was P856, which he developed together with a team from California Technology and Manufacturing. Currently he is in working on 0.18um process development. His email address is shahriar.ahmed@intel.com.

Mark T. Bohr Mark T. Bohr
Mark T. Bohr joined Intel in 1978 after receiving a MSEE from the University of Illinois. He has been a member of the Portland Technology Development group since 1978 and has been responsible for process integration and device design on a variety of DRAM, SRAM, and logic technologies, including recently 0.35um and 0.25um logic technologies. He is an Intel Fellow and director of process architecture and integration. He is currently directing development activities on 0.18um and 0.13um logic technologies. His email address is mark.bohr@intel.com.

Scott Thompson Scott Thompson
Scott Thompson joined Intel in 1992 after completing his Ph.D. under Professor C. T. Sah at the University of Florida on thin gate oxides. He has worked on transistor design and front-end process integration on Intel's 0.35, 0.25, and 0.18um silicon process technology design for the Pentium® and the Pentium® II microprocessors. Scott is currently managing the development of Intel's 0.13um transistor design. His email address is scott.thompson@intel.com.

Simon Yang Simon Yang
Simon Yang received his B.S. in Electrical Engineering from the Shanghai University of Science and Technology (Shanghai, PRC). He then received his M.S. in Physics and a Ph.D. in Materials Engineering from the Rensselar Polytechnic Institute in New York. He joined Intel after graduating in 1987 and is currently leading transistor and yield improvement for Intel's 0.18um logic technology. His email address is shi-ning.yang@intel.com.

Page 8 of 8


		Adam Brand Adam Brand received his BSEE and his MSEE from the Massachusetts Institute of Technology in 1991. He joined Intel in 1991 and is currently working in the California Technology and Manufacturing 0.25um Device Group. His interests include transistor performance optimization, high voltage device development, and circuit modeling. His email address is adam.d.brand@intel.com.

		Aravinda Haranahalli Aravinda Haranahalli received an MS in Physics in 1976 and a Ph.D in Materials Engineering 1980 from the University of Florida. He joined Intel in 1984 and has held various management positions in technology, manufacturing, and business development. He currently manages interconnect technology development for 0.2um. Before joining Intel he held technology positions at Texas Instruments and Fairchild. His current interests include technology, manufacturing, and business management. His email address is aravinda.r.haranahalli@intel.com.

		Ning Hsieh Ning Hsieh received a Ph.D. in Materials Science from Northwestern University in 1979. He worked for various semiconductor companies including IBM, Fairchild, and DEC. He joined Intel in 1993 and has worked in CTM Technology Development since then. His work experience is mostly in process integration. He has published six external papers and has six patents. His email address is ning.hsieh@intel.com.

		Yi-Ching Lin Yi-Ching Lin graduated from the University of California, Berkeley with a Ph.D. in EECS in 1981. Prior to joining Intel in 1987, he was with Texas Instruments and Monolithic Memories, Inc. He has been working in the area of process integration for microprocessor, Flash and EPROM memories. He had also worked on technology transfer from D2 to foreign foundries, including those located in Taiwan and Japan. His email address is yi-ching.lin@intel.com.

		George E. Sery George E. Sery is an Intel Fellow and director of Device Technology Optimization in Intel's California Technology and Manufacturing group. Mr. Sery is currently responsible for directing process characterization, performance improvement, and capability enhancement for Intel's 0.25 micron CMOS logic technology. He received a B.S. and M.S. in electrical engineering from the University of Minnesota in 1976 and 1978 respectively. He joined Intel in 1978 as part of the SRAM Technology Development group. He has been involved with the development of NMOS and CMOS technologies for logic, SRAM, and Flash memory applications. For each technology, he has led the device physics team responsible for device development and process characterization. His email address is george.sery@intel.com.

		Nicky Stenton Nicky Stenton received a M.S. in Materials Engineering from Lehigh University in 1982. She joined Intel in 1982 and most recently has been working on transistor process development in the California Technology and Manufacturing P856 Integration group. Her email address is nicky.stenton@intel.com.

		Been-Jon Woo Been-Jon Woo received a B.S. in Chemical Engineering from the National Taiwan University in 1975 and a Ph.D. from USC in 1979. She joined Intel in 1984 after working at Fairchild. She has worked in EPROM, Flash, and logic technology integration in the California Technology and Manufacturing group. She is currently the 0.25um transistor integration manager. Her email address is been-jon.k.woo@intel.com.

		Shahriar Ahmed Shahriar Ahmed joined Intel in 1985, initially as an interconnect device engineer working on Process 448. He subsequently was part of the team that developed P648 and coordinated the final transfer to high-volume manufacturing. Shahriar then moved on to be the device engineer for Intel's first bi-CMOS process. His next project was P856, which he developed together with a team from California Technology and Manufacturing. Currently he is in working on 0.18um process development. His email address is shahriar.ahmed@intel.com.

		Mark T. Bohr Mark T. Bohr joined Intel in 1978 after receiving a MSEE from the University of Illinois. He has been a member of the Portland Technology Development group since 1978 and has been responsible for process integration and device design on a variety of DRAM, SRAM, and logic technologies, including recently 0.35um and 0.25um logic technologies. He is an Intel Fellow and director of process architecture and integration. He is currently directing development activities on 0.18um and 0.13um logic technologies. His email address is mark.bohr@intel.com.

		Scott Thompson Scott Thompson joined Intel in 1992 after completing his Ph.D. under Professor C. T. Sah at the University of Florida on thin gate oxides. He has worked on transistor design and front-end process integration on Intel's 0.35, 0.25, and 0.18um silicon process technology design for the Pentium® and the Pentium® II microprocessors. Scott is currently managing the development of Intel's 0.13um transistor design. His email address is scott.thompson@intel.com.

		Simon Yang Simon Yang received his B.S. in Electrical Engineering from the Shanghai University of Science and Technology (Shanghai, PRC). He then received his M.S. in Physics and a Ph.D. in Materials Engineering from the Rensselar Polytechnic Institute in New York. He joined Intel after graduating in 1987 and is currently leading transistor and yield improvement for Intel's 0.18um logic technology. His email address is shi-ning.yang@intel.com.