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Source/Drain Engineering

In this section, we investigate the scaling of source/drain extension (SDE) depth and gate overlap for MOSFETs of 0.1um and below. For the purposes of this discussion, the SDE is the shallow diffusion that connects the channel with the deep source and drain. Junction depth always refers to the SDE junction depth. The deep source/drain junction depth is held constant. Overlap is defined as the distance the SDE extends under the gate. The metallurgical spacing (L_MET) is the distance between the source and drain SDE (see Figure 9).

We show that a minimum SDE to gate overlap of 15-20 nm is needed to prevent degradation of drive current (I_DSAT). We also show that scaling SDE vertical depths below 30-40 nm results in little to no performance benefit for 0.1um devices and beyond. This is because any improvement in short channel effects due to reduced charge sharing is offset by a large increase in external resistance and too small an overlap between the SDE and gate.

Figure 9: Terminology used in this discussion

Shallow Junction Formation

Very short gate length transistors with shallow SDE junctions and small gate overlap have been reported [11,12]. Many of these transistors have lower than expected drive currents given their extremely short channel lengths. We propose that these low drive currents are the result of an SDE that is too shallow and therefore leads to a high external resistance and too small of an overlap between the SDE and gate. Junction depths are currently 50-100 nm for 0.25um process technologies and are predicted to be as low as 10 nm for future deep sub-micron devices (see Figure 10). The fabrication of these shallow junctions is less of an issue than whether or not the shallow junctions offer any device benefit. Shallow junctions can be fabricated by carefully controlling transient enhance diffusion (TED) [13-17]. Methods for reducing TED include lowering implant energies, amorphization followed by solid phase expitaxial regrowth and high temperature, and short time rapid thermal anneal cycles. Figure 11 shows an example of a shallow 35 nm junction formed by a low energy implant and a rapid thermal anneal. Alternate architectures such as removable spacer process flows can also be used to minimize SDE depths. In this architecture, an initial disposable spacer is used. High temperature cycles for forming the S/D and doping the poly-Si gate are used before the introduction of the SDE structure. These cycles permit the use of extremely low temperature anneal cycles engineered to minimize SDE junction depths and maximize dopant concentrations.

Figure 10: SIA roadmap for junction depth

Figure 11: Shallow 30.0 nm SDE formed by a low
energy implant and rapid thermal anneal

SDE Junction Scaling

Reducing SDE junction depths will improve device short channel characteristics by reducing the amount of channel charge controlled by the drain. This may not, however, lead to improved device performance. Figures 12a and 12b show the potential contours for two devices with junction depths of 30 and 150 nm, respectively, biased in the off-state condition. In this figure, the potential contours extend much further into the channel for the device with the deep junction.

Figure 12: Potential contours for two devices biased in
an off-state condition (a) 30 nm shallow junction and
(b) 150 nm deep junction

Thus, transistors with deeper junctions will have worse short channel characteristics. Unfortunately, shallow SDE junctions can increase the external resistance of the device. Figure 13 shows the various components of external resistance for a MOS device. Current flows from the channel inversion layer into the SDE accumulation region (R_ACCUMULATION). The current then spreads out into the SDE (R_SPREADING) region and through the bulk SDE area (R_SHUNT). The final component of resistance is associated with the deep source/drain and salicide (R_CONTACT). In deep sub-micron devices, particularly NMOS, the SDE accumulation and spreading components are the dominant components of external resistance. The components associated with the SDE region become a greater problem as the transistor feature size is scaled (channel length and SDE depth reduced) since the scaling reduces channel resistance while increasing the components of SDE resistance.

A second scaling limit is the minimum SDE-to-gate overlap for a device. Reducing this overlap causes the current to spread out into a lower doping location of the SDE. This can strongly increase accumulation and spreading resistance and increase the total external resistance. For example, if the overlap is zero, the current flow would spread out at the gate edge where the SDE doping concentration would be zero. In the next section, we investigate scaling limits for SDE to junction depth and gate overlap.

Figure 13: Components of external resistance

Minimum SDE-to-Gate Overlap

The test structure shown in Figure 14 is used to evaluate the effect of SDE-to-gate overlap on I_DSAT. In this test structure, the SDE implant is performed after the formation of a thin offset spacer. By varying the thickness of the offset spacer, the SDE-to-gate overlap and vertical junction depth can be independently varied. The transistor data presented are measured on devices with a process flow similar to our 0.25um technology [2].

Figure 14: Test structure to evaluate minimum
SDE-to-gate overlap

Also included is data on transistors with gate length, gate oxide, and power supply scaled by 0.7 and (0.7)² from our 0.25um technology. All transistors have controlled sub-threshold slopes of less than 85mV/decade, 1nA/um off-state leakage, and electrical channel lengths (L_E) between 0.06 and 0.14um.

With the above test structure fabricated for a range of poly-Si gate lengths, the transistor saturation drive current versus the SDE overlap for both fixed vertical SDE depth and fixed SDE metallurgical spacing was measured. The SDE metallurgical spacing is kept constant by adjusting the poly-Si gate length to maintain 1nA/um off-state leakage. Figure 15 shows the vertical SIMS profile of an SDE junction used in the experiment (1.0e15cm^-2, 5keV arsenic implant RTA annealed). Figure 16 shows the effect of spacer offset on overlap capacitance and I_DSAT. For spacer offsets greater than 40 nm, there is a flattening in overlap capacitance implying minimal SDE-to-gate overlap. A degradation in I_DSAT is also clearly observed for offset spacer widths greater than 20 nm.

Figure 15: Vertical SIMS profile of Arsenic SDE

Figure 16: I_DSAT and C_MILLER versus spacer offset

The lateral diffusion of the SDE junction under the gate edge is estimated to be 0.6 - 0.7 times the vertical depth minus the offset spacer width. This estimate is obtained from process simulations and junction-staining measurements. Experimentally, the offset spacer width is varied from 0 to 40 nm and is used to modulate the SDE-to-gate overlap from approximately 40 to 0 nm. Figures 17 and 18 show I_DSAT versus SDE overlap for both NMOS and PMOS 0.25um devices as well as the 0.7 scaled devices. These figures also show that, independent of the feature size of the process technology, a degradation in I_DSAT is observed if the overlap is less than 15-20 nm.

Figure 17: I_DSAT versus SDE overlap (NMOS)

Figure 18: I_DSAT versus SDE overlap (PMOS)

Minimum SDE Junction Depth

The optimal SDE vertical depth is now investigated. For this set of experiments, both the conventional and removable spacer flows were used. Figure 19 shows NMOS and PMOS drive current versus SDE depth for devices with 1nA/um of off-state leakage. The SDE depths were adjusted by varying the implant energy (500eV - 40KeV) and the RTA temperature. In Figure 19, we see that a maximum in I_DSAT occurs when the vertical junction depth is 35-40 nm. With an SDE deeper than 35-40 nm, short channel effects degrade due to increased charge sharing. This necessitates a larger channel length to meet the off-state criteria and a loss in I_DSAT. SDE depths shallower than 35-40 nm result in degraded I_DSAT due to increased external resistance and an overlap between the SDE and gate that is too small.

Figure 19: I_DSAT versus SDE depth

Simulation results for the above experiment are shown in Figure 20. In this figure, external resistance and short channel behavior (defined by source-to-drain distance at 1nA/um off-state leakage) versus SDE junction depth are quantified.

Figure 20: Simulation data quantifying R_EXT and L_MET
versus junction depth

These results support the conclusion that the observed drive current maximum at a 35-40 nm junction depth results from tradeoffs in short channel effects, external resistance, and SDE-to-gate coupling. Note that these conclusions implicitly assume that the maximum SDE concentration is solid solubility limited for these devices.

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