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INTRODUCTION

The need for high-density interconnects in a cost-effective flip-chip package was the motivation for FCPGA technology development. This paper describes the challenges encountered during the first generation FCPGA package design, validation, assembly processes, and material development.

FCPGA was designed as a socketable solution. The pin side view of an FCPGA package is shown in Figure 1. The use of the existing 370 socket infrastructure helped with the OEM acceptance of this new package.

The key features of the FCPGA technology are as follows:

1. Stackup

   The substrate is comprised of an FR-5 equivalent core with two resin build-up layers on each side. Both blind and buried vias are used to ease package routing.

2. Bump Pitch

   The flip-chip interconnects are built on an organic substrate with a solder bump pitch of 11 mils (279.4 µm).

3. Decoupling Capacitors

   Pin side decoupling capacitors were added to lower the power supply loop inductance.

4. Surface Mount Package Pins

   SMT pins were used to ease package routing. This was an improvement over through hole mounted pins. The use of SnSb solder to join the package and pins provided solder joint reliability through subsequent reflow operations.

Figure 1: Pin side view of the FCPGA package

Package Design and Validation Overview

Package Designs
Several test vehicles and test structures were designed and analyzed to validate the package's electrical, thermal, mechanical, and reliability performance. Key attributes of several packages are tabulated in Table 1 [2, 3, 4, 5].

The layer structure of an FCPGA substrate is displayed in Figure 2; the targeted thickness of each layer and package key feature sizes are given in Table 2.

Figure 2: Cross section of FCPGA substrate

One of the resistance test structures built into the test packages is shown in Figure 3; four point probing was used for the resistance measurement. Multiple via chains and conductor sheet resistance data confirmed that the package manufacturing process was capable of meeting targeted specifications. In order to ensure impedance values satisfied the data bus requirements, dielectric constants across a wide range of frequencies were analyzed and measured. The comparison between modeled and measured values is shown in Figure 4. The empirical data is in good agreement with analytical prediction.

Figure 3: FCPGA resistance test structure

Figure 4: Comparison of calculated and measured dielectric constants in various frequency ranges

Thermal Performance
Both modeling and testing were conducted to validate the FCPGA thermal solutions. With increasing core speed and maximum power dissipation, both passive and active heat sinks were evaluated. Details of the thermal design challenges are discussed in the Thermal Designs section of this paper.

Mechanical and Package Reliability
Mechanical tests and modeling were performed to address concerns about the structural integrity of the FCPGA package. A total of 100 FCPGA samples were tested with uniform and edge-loaded forces (20 to 100 lbs). Visual inspection and post-stress electrical test data confirmed that there was no change in the mechanical and electrical integrity of the package. Moreover, an additional 40 samples were uniformly loaded up to 100 lbs. and subjected to 600 cycles of T/C "B." No sign of failures was seen, and the chip cap solder joint strength retained a healthy level as illustrated in Figure 5.

Figure 5: Chip capacitor solder joint shear strength distribution at end-of-line, 300 and 600 cycles of T/C "B"

The collected data on maximum package/die loading and chip cap solder joint shear strength confirmed the robustness of the FCPGA package. Various stresses specified for Intel assembly technology certification (such as Temperature Cycling, Bake, Power Cycling, Shock, and Vibration, etc.) were performed to accelerate other possible failure mechanisms. Several failure modes (such as metal migration and weak pin solder joint) were observed early on, but fixes were quickly implemented, which eliminated these issues. In conclusion, there were no high-risk issues that appeared during testing that impacted the technology certification.

Continuous data was collected at Intel and at supplier manufacturing sites. This included electrical, mechanical, and thermal measurements. These data, collected since early in the development phase, built sufficient confidence that the FCPGA package was a viable packaging solution for current as well as future microprocessors.