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FCPGA KEY CHALLENGES

Thermal Designs
Thermal design solutions for the FCPGA package pose challenges because of the system chassis spatial constraints and the need to meet maximum power dissipation requirements. The design was also challenging because a heat sink ground feature that suppresses potential electromagnetic emission had to be integrated into the package. The key thermal design constraints are listed in Table 3. To broaden the variety of possible FCPGA package applications, both passive and active heat sink designs were evaluated. A schematic of passive and active heat sink solutions is shown in Figures 7 and 8. Preliminary empirical and modeling results suggested that passive and active solutions could support power of about 19W and 22W, respectively.

Figure 7: Schematic of an active heat sink solution

Figure 8: Schematic of a passive heat sink solution

High-Speed Bus Impedance Requirement
High-speed digital systems have problems that manifest themselves in three distinctive ways. First, conductor traces can experience reflections due to multiple impedance mismatches. Second, cross talk may occur because of unwanted electromagnetic coupling between adjacent traces. Third, ground bounce can be significant due to inductance in the ground return path of the IC package. The combined result of these effects could adversely impact timing margins in systems and thus limit the ultimate performance of the system. In the FCPGA package, a good deal of effort was put into controlling the impedance to limit the impact of the first problem.

The design of a fixed-impedance bus structure makes it more sensitive to the physical dimension tolerances in the manufacture of the package. The FCPGA design rules will support multiple impedance targets in the package. The bus impedance specifications call for a tolerance target of +/- 10%.

Impedance is a function of dielectric layer thickness, dielectric constant, and Cu trace width. This requires rigorous tolerance control of dielectric thickness. Nonuniformity in thickness of the Cu plating will directly add variability to the thickness of the dielectric layer between two adjacent Cu layers. Since there is inherent Cu thickness variation, the control of dielectric layer thickness variation becomes even more stringent.

Initial data indicated this variation would be a challenge for the FCPGA package as there was a higher dielectric thickness variance than desired, and a correspondingly variable impedance value. However, as illustrated in Figure 9, impedance (Zo) measurements taken after process improvements showed that the mean impedance stabilized. The improvement was made possible through improving the Cu thickness uniformity and by making a smoother insulator surface.

Figure 9: Impedance measurements with two different dielectric thicknesses

µ-Via Reliability Issues
Preliminary reliability data showed m-via delamination. The m-via delamination resulted in a high-percentage fall off after 300 cycles of T/C "B" (-55C <-> 125C) stressing and higher cumulative fails after 1000 cycles of T/C "B". Figure 10 shows an example of a delaminated via that caused an electrical failure.

Figure 10: Example of a delaminated via

Failure analysis suggested that via delamination occurred at the interface between the electrolytic Cu and electroless Cu layers. Hot oil thermal shock tests were utilized as a quick-turn reliability monitor. The measurement of improvements in the manufacturing process were based on the shifts in the m-via resistance. Test data confirmed that two factors were the significant modulators in m-via delamination. Figure 11 shows a schematic drawing of various via structures, as well as the test data for m-via resistance shift after hot oil thermal shock. The test results clearly indicated that via resistance increased more than 50% after thermal shock for some test structures. After process fixes were implemented, no via resistance shift was seen after 400 cycles of stress!

Figure 11a : Schematic of various via structures

Figure 11b: Via resistance before process fix

Figure 11c: Via resistance after process fix

The improvement in via integrity was also verified through via "pop" tests. Three types of failure modes were observed and are shown in Figure 12. None of these failure modes appeared on FCPGA packages after the process fixes were implemented.

Figure 12a: Schematic of a PTH via structure

Figure 12b: Popped via failure indicating weak bonding at the two Cu layers interface on package before process fix

Figure 12c: Broken via edge indicating strong Cu layer interface on package after process fix

Figure 12d: Broken via plug plating indicating strong bonding at the two Cu layers interface after process fix

SMT Pin Development
The FCPGA package utilizes SMT butt-mounted pins on an organic substrate. To determine the reliability of these pins, experiments were conducted to evaluate different combinations of pin solder joint structures. They were made from three solder materials, three different solder volumes, skew misalign pins, and smaller pin nail-head sizes. The attributes of each leg of the experiment are detailed in Table 4. Additionally, pin pull and pin shear testing were used to quantify the pin strength before and after stresses.

Table 4 : SMT pin strength attributes

Test data confirmed that the smaller pin nail heads and intentional pin misalignment had lower pin strength as measured before assembly. Legs with M mg and H mg of SnAg and SnSb legs showed comparable pin pull strength and pin shear strength with the exception of the L mg SnAg lot, which had lower pin pull and pin shear strength. Interestingly, after assembly, the SnAg lots' pin pull strength was reduced significantly. Both SnSb (A%) and SnSb (B%) lots showed no sign of pin joint strength degradation after assembly. The SnSb (B%) was selected as the POR material because SnSb (A%) required a higher reflow temperature, which was undesirable.

Low Cost Underfill Material and Process Development [7]
The use of a two-step process and two separate materials for underfill and fillet in C4-OLGA packages resulted in high equipment costs and a narrow process window. The challenge in FCPGA was to develop a low-cost, but high-performance underfill material that would enable a simplified process and deliver high yields and improved unit per hour (UPH) capability.

Underfill material selection criteria included raw material cost, manufacturability, reliability and process integration performance, and supplier technical support and quality. The underfill development team also reexamined the reliability and manufacturability success criteria such as alpha particle counts and the number of voids and voiding sizes, used in previous stages of development.

In developing the new underfill process, viscosity and self-fillet formation are two key epoxy material properties. Based on material data sheets provided from fourteen suppliers worldwide, a total of four different materials was chosen for further evaluation. Score cards from each of the candidates were assessed to collect technical, business support, and quality data. Based on the collected information, the POR underfill material was then selected. After the POR material was finalized, the epoxy module engineering team focused on underfill process optimization. Collaborative effort from the development team resulted in an optimized and simplified underfill flow that met the FCPGA cost targets.

Figure 13: A comparison of the C4-OLGA and the FCPGA underfill processes

Figure 13 illustrates the differences between the C4-OLGA and the FCPGA underfill process flows. As shown in the POR flows, the FCPGA process has one, instead of two, dispensers and a BTU, which could save on equipment expenditures. Moreover, when results were evaluated, the FCPGA also improved the yield, and it had higher UPH throughput. The simplified underfill process, together with the high performance of the underfill material, was a plus for the FCPGA program.

Flip-Chip Solder Bump Non-Wet
Initial FCPGA data collection indicated the highest pareto of yield loss was attributed to open failures due to the non-wet of the C4 bumps. Low yield analysis revealed that the non-wet falls into two categories:

• edge non-wet, raccoon tail type, which can be detected with X-ray

• center non-wet, which is invisible with X-ray

A root cause assessment of the center non-wet showed no correlation between the microprocessor chip's passivation oxide thickness or coplanarity, the substrate's bump oxide, flux quantity, or uniformity during the chip attach process. A cross section of the center non-wet unit's solder bump joints revealed the substrate's and chips' bumps were not adequately aligned, except for those at the middle of the die. The right and left sides of the bump joints were slightly misaligned at opposite directions. Because of these observations, a failure mechanism for center non-wet was proposed; as illustrated in Figure 14, it turned out that the lack of bump coplanarity in the substrate prevented solder joints from forming at the center region of the die. This model also explained the slight shift in the alignment of the substrate's and die's bumps near the edge of the die.

Figure 14: Proposed center non-wet mechanism; excessive substrate bump coplanarity prevents solder joints from forming at the center area of the die

The proposed model was validated through experimentation. From the data, we also realized that a maximum substrate bump coplanarity was required to prevent center non-wet. This has been defined in the specification for incoming packages.