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SIGNAL INTEGRITY CHALLENGES AND SOLUTIONS

The challenge in designing a package with good signal integrity lies in properly selecting a technology and appropriately designing with that technology such that characteristic impedance, resistance, crosstalk, and SSO are controlled. These aspects of a package are related to fundamental choices such as the materials used. The ability to control the manufacturing process is also key to controlling these parameters within certain ranges. Finally, good design practices are necessary to ensure an optimized design that meets performance requirements.

Characteristic Impedance
Characteristic impedance is a term borrowed from transmission-line theory and is, at a very academic level, the ratio of the electric-to-magnetic field distribution in a transmission line, where a transmission line is a multi-conductor structure that propagates a signal [1]-[4]. Package and system designers are concerned about this characteristic of the I/O traces in the system because signal reflection occurs at any boundary where there is a change in characteristic impedance. The amount of reflection is directly proportional to the difference in impedances at the boundary according to

   (1)

where

Reflection degrades signal integrity and is a primary cause of phenomena such as ringback and over/undershoot. The emphasis in I/O interconnect design is, therefore, on matching the impedance throughout the path of the I/O interconnect.

Figure 9: Package trace configurations

Although closed form solutions for characteristic impedance exist for certain configurations that are very similar to the designs used in traces in Intel’s packages, these formulas are for aspect ratios of trace width to plane separation that are different from those of Intel’s packages. The formulas, therefore, yield Z₀ values that are not very accurate in many cases. The preferred method of solving for Z₀ is to use a software tool that solves Maxwell’s electromagnetic field equations. Z₀ can be measured in the lab using time-domain reflectometry (TDR). Frequency-dependent characteristics can be extracted using network analyzer measurements. Figure 9 illustrates the different designs used for traces in package substrates. If power/ground planes are above and below the trace, the structure is called a "stripline." If there is only one plane nearby, it is called a "microstripline." If the structure also contains shielding traces tied to ground on either side of the trace, it is called a "coplanar waveguide." The stripline configuration is the preferred configuration because the presence of two planes allows for better impedance control, provides higher bandwidth, and affords better isolation of signals from other parts of the package and system. Figure 10 shows a more detailed depiction of a stripline structure.

Figure 10: Stripline configuration

There are two items of concern in package design regarding Z₀. The first is being able to target a specific characteristic impedance, and the second is being able to control that impedance within a certain tolerance of the target value. The target value is usually set by matching to the system impedance, which is usually 50 ohms. Special bus protocols may require matching to an impedance other than 50 ohms. Sometimes matching to two or more different impedances within a package is required. The challenge in package design is, thus, to be able to target two or more impedances in a package and to be able to control that impedance within increasingly tighter tolerances. Variation in impedance is caused by manufacturing variations and differences in the topology of the routing in the package substrate. Since manufacturing variation will always be present, Intel has focused during package development on understanding the impact of the packaging technology and design on the target impedance and variation and on coming up with new designs to control these.

One example of a design innovation used to control impedance variation can be found in the packaging for the Pentium® II brand. In the original organic flip-chip packaging used for this product line, the power and ground planes above and below signal routing layers had degassing holes arranged periodically throughout the planes. These degassing holes were necessary for manufacturing reasons. The requirement was that there be a certain density of holes spread evenly throughout the planes, so routing above and beneath these holes was unavoidable. Originally, the degassing holes were aligned among all planes such that some traces were routed beneath solid metal and some beneath holes, as shown in Figure 11. This led to large impedance variation (~20%) due to routing variation. Investigations were made to develop an optimized degassing hole pattern such that the impedance variation would be minimized [5]. The optimized pattern is shown in Figure 12 and consists of a staggered, rotated pattern where any trace routed between these planes will "see" the same degassing hole pattern and, thus, have a very similar impedance to other traces routed on the same layer. Using this pattern, our analysis showed that the variation due to routing was reduced to <3%.

Figure 11: Old degassing-hole pattern

Figure 12: New degassing-hole pattern

Trace Resistance

After characteristic impedance, trace resistance is the next challenge faced in designing a package with good signal integrity. Resistance is a fairly easy concept to comprehend; yet, I/O package interconnect resistance has already been a concern on recent products and will continue to be an issue for future products. Resistance (R) of a structure is easily calculated by

where

One of the challenges has been to obtain accurate values for r . The copper used for traces in Intel’s packages is not pure copper; thus, the resistivity value is not easily obtainable from published literature. Much focus is given to obtaining accurate values for r during the development cycle by using test structures that are measured both internally and monitored continuously during process development at the suppliers. On top of the difficulty in obtaining accurate material parameter data for trace resistance, the inherent limitations of the materials used for package traces is a concern for future-generation package technologies. The reason is that trace widths are decreasing as die and package dimensions decrease, which increases the trace resistance. At the same time, voltage levels, and, thus, the allowable DC voltage drop through a package, are decreasing. These contradictory trends will prove to be a challenge that will need to be overcome in future package technology development.

Crosstalk
Impedance control and trace resistance are signal integrity characteristics of a package that are of concern for single-bit switching. The remaining signal integrity characteristics, crosstalk and SSO, are of concern for multiple-bit switching. Crosstalk is the term used to refer to unwanted signal coupling between lines. Crosstalk is a complex function of the characteristics of the driver and receiver, trace characteristics, and switching patterns; however, certain generalities regarding package design and its relationship to crosstalk can be made. Crosstalk in a package is dependent upon the stack-up, just as is characteristic impedance; however, crosstalk is primarily affected by the distance between traces, by the amount of parallelism between traces, and by the presence of reference plane discontinuities. The longer the parallel distance between two or more lines, the higher the crosstalk between them. Also, the closer the lines are to one another, the higher the crosstalk. The proximity of power/ground planes to the traces can help reduce crosstalk as long as these planes do not have discontinuities in the proximity of the traces. Reference plane discontinuities contribute to increased crosstalk levels for traces routed above or beneath these planes. For continuous reference planes, crosstalk is directly proportional to the distance between the planes above and below the trace.

There are no simple formulas for predicting crosstalk. Models of the traces, with the mutual inductance and capacitance calculated, must be generated and simulations run using buffer models and models representing the system loads to correctly determine the amount of crosstalk in a package design. There is a quick rule of thumb that can be used to approximate the amount of crosstalk expected in a package substrate or motherboard routed in a stripline configuration. Using the ratio of S/H, where S is the trace spacing and H is the distance from the trace to the power/ground plane above or below (assuming the traces are centered between the planes), the approximate crosstalk percentage is as follows [6]:

• if S/H > 1, crosstalk < 50%
• if S/H > 3, crosstalk < 10%
• if S/H > 4, crosstalk < 5%
• if S/H > 5, crosstalk < 1%

To meet today’s product performance requirements, package-level crosstalk must be less than 10%, which means that S/H should be greater than 3. For today’s flip-chip technology, S/H is only slightly above 1 for the minimum trace spacing achievable with the technology, which means that the technology capabilities are beyond what can be practically used by the product. By design, on some products, Pentium® 4 processors for example, the traces need to be spaced farther apart than the minimum spacing capability of the technology.

I/O Return Path
The final critical element of I/O interconnect design is the return path and the associated manifestations of a poor return path. "Return path" refers to the power and/or ground path that an I/O uses for reference, from which it draws current. This is a complex topic, and this paper cannot begin to do it justice. There are some best known methods (BKM’s) and guidelines, which have been gathered as a result of experimentation and solutions of problems on recent products, which can be used to guide designers. Many of these are discussed in this section.

One manifestation of a poor return path is "SSO pushout". SSO pushout refers to the difference in timing between single-bit and multiple-bit switching. This is one of the items that system designers need to budget for up front in the design. Essentially, they need to identify the worst-case switching that the system will have to support and ensure that the design is robust enough to do this. Although there are many contributors to SSO pushout, recent validation work on the Pentium® II processor points to a large inductive return path as being a primary contributor.

Because it is difficult to model many return-path complexities, especially in the design phase when the layout is not frozen, a growing list of BKMs for avoiding potential problems is being formulated in the I/O interconnect design community at Intel. At the package level, the guidelines are as follows:

• Design a symmetric pinout with as low an I/O to power/ground pin ratio as possible within the pin budget for the package size. For example, in Figure 13, pinout A is better than pinout B because A is more symmetric.

Figure 13: Pinout example

• Ensure that each signal has a clearly defined return path from the die to the land.
• Avoid voids or discontinuities in the return path.

Some general system BKM’s, which should be used at each level of design, have also been developed [7]:

• Avoid signal lines that change reference planes, i.e., are referenced to ground in one part of the design and power in another part.
• Avoid referencing signal lines to power only, with no ground reference.
• Avoid transitioning from dual-referenced signals in one part of the design to single-referenced signals in another part of the design.
• Avoid referencing a signal to a power/ground reference that is not the primary reference for that signal. For example, there are often multiple power planes in a package. A signal must be referenced to the power plane that is supplying power for that signal not just to any power plane in the package.
• Avoid routing signal lines so that they cross splits in a reference plane.
• Avoid referencing lines to shielded lines that are floating or not adequately tied to power/ground with multiple vias.
• Avoid routing over voids in the plane, e.g., via voids in the ground plane.