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Memory Validation:
DDR3 DRAM Components
DDR3 1333/1066/800MHz DRAM Component-level Validation results
Results of a small sample of DDR3 DRAM components tested using Verigy 93000 Tester and Vector Network Analyzer.
AMB/FBDIMM Validation Procedures
Advanced Memory Buffer(AMB) and Fully Buffered Dual In-line Memory Module(FBDIMM) Validation Procedures
View FBDIMM and AMB validation overview information.
Advanced Memory Buffer Components
Advanced Memory Buffer(AMB) Component Validation results
Results of a sample of AMB components assembled on FBDIMMs.
Fully Buffered Dual In-line Memory Modules
Fully Buffered Dual In-line Memory Module(FBDIMM) Validation results
Results of a sample of FBDIMMs.
DDR2 DRAM Components
DDR2 800 MHz DRAM Component-level Validation Results
Results of a small sample of DDR2 DRAM components tested using Agilent 93000 Tester and Vector Network Analyzer*.
DDR2 667 MHz DRAM Component-level Validation Results
Results of a small sample of DDR2 DRAM components tested using Agilent 93000 Tester and Vector Network Analyzer*. This list now includes 667MHz x4 DRAM for use on FBDIMM.
DDR2 533/400 MHz DRAM Component-level Validation Results
Results of a small sample of DDR2 DRAM components tested using Agilent 93000 Tester and Vector Network Analyzer*. This list now includes 533MHz x4 DRAM for use on FBDIMM.
Unbuffered DIMM
DDR3 1333/1066/800 MHz Non ECC Unbuffered DIMM System-level Validation Results
Results of a small sample of Non ECC DDR3 1333/1066/800 MHz Unbuffered DIMMs tested on on Intel® X38 Chipset based reference platform(s).
DDR3 1066/800 MHz Non ECC Unbuffered DIMM System-level Validation Results
Results of a small sample of Non ECC DDR3 1066/800 MHz Unbuffered DIMMs tested on on Intel® G33 Chipset based reference platform(s).
DDR2 800 MHz Non ECC and ECC Unbuffered DIMM System-level Validation Results
Results of a small sample of Non ECC and ECC DDR2 800 MHz Unbuffered DIMMs tested on reference platform(s).
DDR2 667 MHz Non ECC & ECC Unbuffered DIMM System-level Validation Results
Results of a small sample of Non ECC and ECC DDR2 667 MHz Unbuffered DIMMs tested on reference platform(s).
DDR2 533/400 MHz Non ECC & ECC Unbuffered DIMM System-level Validation Results
Results of a small sample of Non ECC and ECC DDR2 533/400 MHz Unbuffered DIMMs tested on reference platform(s).
SODIMM
DDR3 800/1066 MHz Unbuffered SODIMM System-level Validation Results
Results of a small sample of DDR3 Unbuffered SODIMMs tested on reference platform(s).
DDR2 800 MHz Unbuffered SODIMM System-level Validation Results
Results of a small sample of DDR2 Unbuffered SODIMMs tested on reference platform(s).
DDR2 667 MHz Unbuffered SODIMM System-level Validation Results
Results of a small sample of DDR2 667 MHz Unbuffered SODIMMs tested on reference platform(s).
DDR2 533/400 MHz Unbuffered SODIMM System-level Validation Results
Results of a small sample of DDR2 Unbuffered SODIMMs tested on reference platform(s).
RDIMM
DDR2 400 MHz Registered DIMM System-level Validation Results
Results of a small sample of DDR2 registered DIMMs tested on reference platform(s).
DDR2 Specifications
Intel Spec Addendum Rev 1.1 for the JEDEC DDR2 667/800 Specification
Intel Spec Addendum Rev 1.1 for the JEDEC DDR2 667/800 Specification in Adobe Acrobat* format.
Intel Spec Addendum Rev 1.0 for the JEDEC DDR2 400/533 Specification
Intel Spec Addendum Rev 1.0 for the JEDEC DDR2 400/533 Specification in Adobe Acrobat* format.
Validation Procedures
Overview
The objective of the validation process is to enable a smooth and quick integration of DDR2-based systems.
DIMM Validation Process
The objective of the Intel validation program for DDR, DDR2, and DDR3 is to verify DDR SDRAM compliance to the Intel specifications for DDR/DDR2/DDR3 and performance of DDR/DDR2/DDR3 DIMM modules in Intel reference systems, so as to provide a guideline for memory compatibility with Intel* chipsets.
DDR Archive
DDR Archive pages
The objective of this archive is to keep the previous generation Intel chipset based validation results accessible to users.
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