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PCI Express* Technology Advancement
Geneseo Technology
 
Overview Description
 
Data- and compute-intensive tasks such as real-time media processing, advanced mathematical modeling and content processing have created a robust market for devices and software known as accelerators. As these specialized accelerators become an increasingly common way of offloading advanced processing from general-purpose CPUs, the methods by which they attach to systems must advance as well. Because a large majority of accelerators on the market today attach via PCI Express* (PCIe), Intel and IBM are proposing a series of significant improvements to the PCIe framework that will allow it to remain a platform for accelerator innovation across markets, systems and functions. These improvements are gathered together under the codename Geneseo.
As with the move from PCI to PCIe, Geneseo is intended to minimize the cost and complexity of transition by utilizing existing hardware without changes to operating systems or applications currently interfacing with PCIe.
 
 
The specific improvements proposed by IBM and Intel
to the PCI Special Interest Group (PCI-SIG) include:
 
Improvement Benefit
Improved bandwidth efficiency New semantics for transferring large data payloads will help accelerators reach peak performance on information-intensive tasks.
Faster link acquisition for high-priority transmissions Enhance QoS flexibility and prioritization of accelerator tasks by providing a way to interrupt lower-priority transmissions without disrupting their completion.
Efficient & reduced latency accesses Changes to PCIe semantics to provide data pre-fetch and caching hints for efficient and low-latency memory access.
Reduced synchronization overhead The need to constantly synchronize memory between an accelerator and a CPU creates overhead. Revised Read-Modify-Write semantics in Geneseo will significantly improve the efficiency of this process.
"Loose" transaction ordering Loosely ordered transactions allow more efficient use of memory and enable applications with irregular memory access patterns to carry them out safely. Geneseo will provide a loose ordering mechanism through transaction-level attributes and hints within the Root Complex.
Dynamic power/thermal control More powerful accelerators will use more power and give off more heat. Geneseo will support dynamic performance/power balancing modes through standard platform configuration mechanisms.
Software model An enhanced software stack will take a full advantage of Geneseo defined hardware capabilities. It will allow more streamlined interaction between accelerator hardware and platform software, enabling Geneseo accelerators to use existing PCIe driver structures to initialize and manage devices. It will also have a highly streamlined application/accelerator interaction, with low system and software latency and overhead.
Improved bandwidth The increased signaling speed of the link will provide almost double the effective bandwidth for the next generation applications while maintaining backward compatibility with the Gen1 and Gen2 devices.
 

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